Sony MHC-VX3 (serv.man2) Service Manual ▷ View online
53
Pin No.
Pin Name
Function
41
TE
I
Tracking error signal input
42
CE
I
Center servo analog input
43
RFDC
I
RF signal input
44
ADI0
O
Test pin (Not used)
45
AVSS0
—
Analog ground
46
IGEN
I
Power supply pin operational amplifiers
47
AVDD
—
Analog power supply
48
ASYO
O
EFM full swing output
49
ASYI
I
Asymmetry comparate voltage input
50
RFAC
I
EFM signal input
51
AVSS1
—
Analog ground
52
CLTV
I
Control voltage input for master VCO
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge-pump output for master PLL
56
AVDD1
—
Analog power supply
57
BIAS
I
Asymmetry circuit constant current input
58
VCTL
I
Control voltage input for variable pitch PLL
59
V16M
I/O
16.9344MHz output (Not used)
60
VPCO
O
Charge-pump output for variable pitch PLL (Not used)
61
DVDD2
—
Digital power supply
62
ASYE
I
Asymmetry circuit ON/OFF
63
MD2
I
Digital-out ON/OFF control
64
DOUT
O
Digital-out output
65
LRCK
O
48-bit slot D/A interface, LR clock output
66
PCMD
O
48-bit slot D/A interface, Serial deta output
67
BCLK
O
48-bit slot D/A interface, bit clock output
68
EMPH
O
Playback disc output in emphasis mode (Not used)
69
XTSL
I
X’tal selection input pin
70
DVSS2
—
Digital ground
71
XTAI
I
X’tal oscillator circuit input
72
XTAO
O
X’tal oscillator circuit output (Not used)
73
SOUT
O
(Not used)
74
SOCK
O
(Not used)
75
XOCT
O
(Not used)
76
SQSO
O
Sub-Q serial output
77
SQCK
I
Clock input for SQSO read-out
78
SCSY
I
Sub-code input
79
SBSO
O
Sub-P through Sub-W serial output (Not used)
80
EXCR
I
Clock input for SBSO read-out
I/O
54
Pin No.
Pin Name
I/O
Function
• VIDEO(1/3)BOARD IC502 MPEG DECODER, MECHANISM CONTROL (M30620MC-A05FP)
1
SENSE
I
Internal state (SENSE) monitor input (IC101)
2
SENSE CLK
O
Serial data reading clock output (IC101)
3
DSP DATA
O
Serial data output (IC101)
4
DSP LATCH
O
Latch output (IC101)
5
DSP CLK
O
Serial data clock output (IC101)
6
TSENS
I
Not used
7
REMOTE IN
I
Not used
8
BYTE
I
External bus width change input (Connected to ground)
9
VSS
–
Ground
10
DSP MUTE
O
Mute output (IC101) “H” : mute
11
CTRL1(L:DOUBLE)
O
Double change output (IC101) “L” : double
12
XRESET
I
System reset input “L” : reset
13
XOUT
O
Main clock output (10MHz)
14
VSS
–
Ground
15
XIN
I
Main clock input (10MHz)
16
VCC
–
+5V power supply
17
NMI
I
Requests mask disable interruption input (Connected to +5V)
18
SCOR
I
Subcode sync input (IC101)
19
D SENS
I
Not used
20
CL680 INT
I
Video CD interruption input (IC505)
21
CL680 HSEL
O
Video CD select data of the host MPU (IC505)
22
DF LATCH
O
Digital filter latch output (IC509)
23
CL680 HRDY
I
Ready signal input for communication to the host MPU (IC505)
24
680 RESET
O
Video CD reset output (IC505) “L” : reset
25
JOG1
I
Not used
26
JOG2
I
Not used
27
CTRL2
O
Double control output (IC101) “H” : double
28
LD ON
O
Laser diode ON/OFF output
29
IIC1
I/O
IIC convertion microcomputer receive data (Former type), IIC clock input from master control (New type)
30
IIC0
I/O
IIC convertion microcomputer transmittion data (Former type), IIC data input from master control (New type)
31
DATA1O
O
Serial 1 data output (IC505, 509)
32
DATA1I
I
Serial 1 data input (IC505, 509)
33
CLK1
O
Serial 1 clock output
34
SHARPNESS
O
Sharpness output L : normal, H : sharpness
35
XVLEVEL. DOWN
O
Fix the video signal output level output
36
SUBQ DATA
I
Serial 2 data input for subcode sync reading
37
SUBQ CLK
I
Serial 2 clock input for subcode sync reading
38
P. ON
I
Not used
39
BUS XRDY
I
Not used
40
BUS
I
Not used
41
BUS XHOLD
I
Not used
42, 43
BUS
I
Not used
44
BUS XRD
I
Model selection input “L” : chinese model, “H” : except chinese model
45
BUS
I
V sync signal input
55
Pin Name
Function
46
BUS XWRL
I
Not used
47
LO. BOOST
I
Not used
48
AUDIO MUTE
O
Audio mute output “L” : mute
49
LOAD OUT
I
Not used
50
LOAD IN
I
Not used
51
INSW
I
Not used
52
OUTSW
I
Not used
53
MODEL 1
I
L : System input (Fixed at “L”)
54
MODEL 2
I
L : System input (Fixed at “L”)
55
TBLL
I
Not used
56
TBLR
I
Not used
57
ENC 1
I
Not used
58
ENC 2
I
Not used
59
ENC 3
I
Not used
60
—
–
Not used
61
—
–
Not used
62
VCC
–
+5V power supply
63
—
–
Not used
64
VSS
–
Ground
65
A7
O
Video mute output “L”
66 to 71
A6 to A1
I
Not used
72
U to I
I
IIC convertion microcomputor transmittion input
73
TEST LED
O
TEST LED for MPEG decoder
74
TEST 1
I
Test mode for Video CD check
75
TEST 2
I
Test mode for servo check
76
TEST 3
I
Not used
77
DEVICE RESET
O
Device system rest output “L” : reset
78
STANDBY
I
Not used
79
FL CS
I
Not used
80
FL
I
Not used
81 to 88
D7 to D0
I
Not used
89
MIC CTRL
I
Not used
90
KEY 1
I
Not used
91
KEY 2
I
Not used
92
KEY 3
I
Not used
93
NY/PAL
I
NTSC/PAL select switch input
94
MUSIC VOL
I
Not used
95
KEY 4
I
Not used
96
AVSS
–
A/D converter ground
97
MODE. SW
I
Not used
98
VREF
I
A/D converter reference voltage input (Connected to +5V)
99
AVCC
–
A/D converter +5V power supply
100
AMP. ON
I
Not used
Pin No.
I/O
56
Pin No.
Pin Name
I/O
Function
• VIDEO(2/3)BOARD IC505 CD DECODER, SYSTEM CONTROL (CL680T-D1)
1
NC
–
Not used
2
VSS
–
Ground
3
CD-BCK
I
CD Decode bit clock
4
CD-DATA
I
CD Decode data
5
CD-LRCK
I
CD Decode Left or Right channel selection clock
6
CD-C2PO
I
CD Decode C2 error data
7
NC
–
Not used
8
NC
–
Not used
9
NC
–
Not used
10
MD0
I/O
Data bus between Microcode ROM/DRAM and CL680
11
MD1
I/O
Data bus between Microcode ROM/DRAM and CL680
12
MD2
I/O
Data bus between Microcode ROM/DRAM and CL680
13
MD3
I/O
Data bus between Microcode ROM/DRAM and CL680
14
MD4
I/O
Data bus between Microcode ROM/DRAM and CL680
15
MD5
I/O
Data bus between Microcode ROM/DRAM and CL680
16
VSS
–
Ground
17
MD6
I/O
Data bus between Microcode ROM/DRAM and CL680
18
VDD3
–
+3.3V Power supply
19
MD7
I/O
Data bus between Microcode ROM/DRAM and CL680
20
VSS
–
Ground
21
MD8
I/O
Data bus between Microcode ROM/DRAM and CL680
22
VDD3
–
+3.3V Power supply
23
MD9
I/O
Data bus between Microcode ROM/DRAM and CL680
24
MD10
I/O
Data bus between Microcode ROM/DRAM and CL680
25
MD11
I/O
Data bus between Microcode ROM/DRAM and CL680
26
MD12
I/O
Data bus between Microcode ROM/DRAM and CL680
27
MD13
I/O
Data bus between Microcode ROM/DRAM and CL680
28
MD14
I/O
Data bus between Microcode ROM/DRAM and CL680
29
MD15
I/O
Data bus between Microcode ROM/DRAM and CL680
30
NC
–
Not used
31
NC
–
Not used
32
NC
–
Not used
33
NC
–
Not used
34
NC
–
Not used
35
NC
–
Not used
36
NC
–
Not used
37
MCE
O
Chip enable signal to Microcode ROM
38
MWE
O
Write enable signal to DRAM
39
VSS
–
Ground
40
CAS
O
Column address strove : Latch the column address to DRAM
41
VDD3
–
+3.3V power supply
42
RAS0
O
Row address strove : Latch row address to DRAM
43
RAS1
–
Not used
44
MA10
O
Address data from CL680 to Microcode ROM
45
MA9
O
Address data from CL680 to Microcode ROM
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