Sony MHC-V818 Service Manual ▷ View online
– 83 –
– 84 –
HCD-V818
8-29. PRINTED WIRING BOARD – CD MOTOR SECTION –
• See page 22 for Circuit Boards Location.
(Page 54)
(Page 54)
– 85 –
– 86 –
8-30. IC BLOCK DIAGRAMS
• CD section
IC101 CXD2545Q
68
67 62 63 64
20 19
C4M
FSTO
XTAI
XTAO
XTSL
VCKI
VPCO
69
C16M
43 PSSL
18
PDO
13
VCO1
12
VCO0
33
PCO
32
FILI
31
FILO
34
CLTV
36
RFAC
38
ASYI
39
ASYO
42
ASYE
73
WFCK
74
SCOR
76
EXCK
75
SBSO
72
EMPH
78
SQCK
77
SQSO
95
MON
94
FSW
96
MDP
97
MDS
26
RFDC
27
TE
28
SE
29
FE
30
25
VC
RFC
CLOCK
GENERATOR
ASYMMETRY
CORRECTION
CORRECTION
DIGITAL
PLL
VARI-PITCH
(
DOUBLE SPEED
)
EFM
DEMODULATOR
TIMING
GENERATOR 1
TIMING
GENERATOR 2
CLV
PROCESSOR
FOCUS SERVO
MIRR
DFCT
FOK DETECTOR
SUBCODE
P-W
PROCESSOR
SUBCODE
Q
PROCESSOR
SERVO
MICRO PROGRAM
INTERFACE
SERVO
AUTO
SEQUENCER
SERIAL
PARALLEL
PROCESSOR
18-TIMES
OVERSAMPLING
FILTER
SWITCH
&
BUFFER
A/D
CONVERTER
SYNC
PROTECTOR
D/A
DATA PROCESSOR
ADDRESS
GENERATOR
PRIORITY
ENCODER
ENCODER
NOISE
SHAPER
MUX
CPU INTERFACE
32K RAM
RESISTER
ERROR CORRECTOR
PEAK DETECTOR
DIGITAL OUT
24
ADIO
21
AVDD
40
AVDD
23
AVSS
35
AVSS
41
ADD
90
ADD
15
DVSS
65
DVSS
81
XRST
22
IGEN
37
BIAS
44
WDCK
45
LRCK
66
FSTI
82
DIRC
83
SCLK
84
DFSW
85
ATSK
98
LOCK
99
SRON, SRDR
1, 2
SFON, SFDR
3, 100
DA01-16
61-46
TFDR, TFON
4, 7
TRON, TRDR
5, 6
FFDR, FFON
8, 11
FRON, FRDR
9, 10
SSTP
16
TES2
14
TEST
17
TES3
TRACKING
SERVO
SLED PWM
GENERATOR
2
TRACKING PWM
GENERATOR
FOCUS PWM
GENERATOR
SLED SERVO
SERVO DSP
PWM GENERATOR
2
2
2
2
2
93 FOK
92 DFCT
91 MIRR
80 SENS
89 COUT
88 CLOK
86 DATA
71 D OUT
79 MUTE
70 MD2
87 XLAT
16
IC102 BA6392FP
BUFF
BUFF
BUFF
BUFF
R
R
F
F
1
CH1 OUT F
2
CH1 OUT R
3
CAPA IN 1
4
CH1 R IN
5
CH1 F IN
6
VREF IN
7
VREF OUT
8
GND
9
CH2 F IN
10
CH2 R IN
11
CAPA IN 2
12
CH2 OUT R
13
CH2 OUT F
14
GND
28 GND
27 CH4 OUT F
26 CH4 OUT R
25 VB IN
24 VS IN
23 VB IN
22 VCC
21 VCC
20 CH3 F IN
19 CH3 R IN
18 CAPA IN 3
17 CH3 OUT R
16 CH3 OUT F
15 MUTE
LEVEL
SHIFT
INTERFACE
BUFF
BUFF
BUFF
BUFF
R
F
R
F
BUFF
INTERFACE
INTERFACE
F
F
R
R
MUTE
IC103 CXA1821M
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LD
VCC
VCC
PD
LD ON
A
LC/PD
B
RFE
C
RFO
D
FE
VEE
FE BIAS
F
TE
E
VC
VC
VC BUFFER
TRACKING ERROR AMP
FOCUS ERROR AMP
RF EQ AMP
APC LD AMP
RF SUMMING AMP
EI
EO
VEE
VCC
VCC
VC
VC
VC
VC
VC
VC
VC
VEE
VEE
VEE
VREF
OSCILLATOR
1/2 VCC
AUTO
RESET
LPF1
MAIN
CONTROL
A/D
20KBIT
SRAM
LPF2
D/A
1
2
3
4
5
6
7
8
9
10
14
13
12
11
CLOCK
RESET
MO
MI
D1
DO0
DO1
VCC
CLOCK
REF
OP2IN
OP2OUT
LPF2IN
LPF2OUT
LPF1IN
LPF1OUT
OP1OUT
OP1IN
CC1
CC2
GND
• MIC/HP section
IC751 M65850FP
2
3
14
1
f04
13 f
12 VCC
11 NC
10 NC
15 f03
5
GND
6
BIAS
C
7
NC
8
NC
9
NC
4
16 f02
17 f01
18 RESET
RESET
C
PREF
LINE
NF
LINE
IN
REFFERENCE
CURRENT
BPF
DET
BPF
DET
BPF
DET
BPF
DET
DET
RESET
Bias
1
2
3
4
5
6
7
8
9
9
10
11
11
12
13
14
15
16
18
17
19
20
21
22
23
24
µ
CON
INTER FACE
ROM
OSC
SOUND
MIX
MIX
GND
VDD
A-OUT
NAR
NC
BUSY
VPP
RST
CH
SD
SI
SI
I4
NC
XT
XT
NC
CMD
NC
ST
I0
I1
I2
I3
NC
• DISPLAY section
IC603 BA3833F
IC851 MSM6653A-517GS-K
• VIDEO section
IC509 PCM1727E
• Deck section
IC602 uPC1330HA
• CD motor section
IC701 M54641L
IC801 BA6286N
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1 CONT
GND
VCC
SW P2 GND
SW R2
1
5
2
7
3
6
4
POWER
AMP.
AMP.
POWER
AMP.
AMP.
CONTROL
INPUT
AMP.
INPUT
AMP.
REG
8
VCC
VCC
REFERENCE
OUT2
OUT1
IN1
IN2
GND
1
2
3
2
3
4
5
6
5
6
7
8
9
8
9
10
TSD
CONTROL
LOGIC
PO WER
SAVE
GND
RIN
VREF
OUT2
OUT2
RNF
GND
VM
VCC
FIN
OUT1
1
2
3
4
5
6
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
POWER
SUPPLY
CLOCK MANAGER
•
DUAL PLL
AUDIO
DATA INPUT
INTERFACE
8 TIME OVER
SAMPLING DIGITAL
FILTER
•
FUNCTION
CONTROL
MODE
CONTROL
MULTI LEVEL
∆Σ
MODULATOR
MULTI LEVEL
∆Σ
MODULATOR
5 LEVEL
DAC
5 LEVEL
DAC
CR LPF
•
OUTPUT
AMP
CR LPF
•
OUTPUT
AMP
BPZ
CONTROL
13
OPEN
XT1
PGND
VCP
NCKO
RSV
SCKO3
ML
MC
MC
RSTB
VOUTR
AGND
VCA
ZERO
BCK
DATA
LRCK
SCKO2
SCKO1
VDD
DGND
XT2
384fs
15
14 VOUTL
CAP
– 87 –
8-31. IC PIN FUNCTIONS
• IC101 DIGITAL SIGNAL PROCESSOR (CXD2545Q)/BD board
Pin Name
SRON
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FFON
VCOO
VCOI
TEST
DV
SS
TES2
TES3
PDO
VPCO
VCKI
AVD2
IGEN
AVS2
ADIO
RFC
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVS1
RFAC
BIAS
ASYI
ASYO
AVD1
DV
DD
ASYE
PSSL
WDCK
LRCK
DATA
BCLK
64DATA
64BCLK
64LRCK
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
–
I
I
O
O
I
–
I
–
I
O
I
I
I
I
I
O
I
O
I
–
I
I
I
O
–
–
I
I
O
O
O
O
O
O
O
Function
Sled drive output (Not used)
Sled drive output
Sled drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Tracking drive output
Tracking drive output (Not used)
Focus drive output
Focus drive output (Not used)
Focus drive output
Focus drive output (Not used)
VCO output for analog EFM (Eight to Fourteen Modulation) PLL (Not used)
VCO input from analog EFM PLL (Ground)
TEST pin connected normally to ground
Digital ground
TEST pin connected normally to ground
TEST pin connected normally to ground
Charge-pump output for analog EFM PLL (Not used)
Charge-pump output for variable pitch PLL (Not used)
Clock input from variable pitch external VCO
Analog power supply
Power supply pin for operational amplifiers
Analog ground
(Not used)
(Not used)
RF signal input
Tracking error signal input
Sled error signal input
Focus error signal input
Center voltage input pin
Filter output for master PLL
Filter input for master PLL
Charge-pump output for master PLL
Control voltage input for master VCO
Analog ground
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparate voltage input
EFM full swing output
Analog power supply
Digital power supply
Asymmetry circuit ON/OFF
Audio data output mode selection input
48-bit slot D/A interface. word clock. (Not used)
48-bit slot D/A interface. LR clock.
DA 16 output when PSSL=1. 48-bit slot serial data when PSSL=0
DA 15 output when PSSL=1. 48-bit slot data when PSSL=0
DA 14 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
DA 13 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
DA 12 output when PSSL=1. 64-bit slot data when PSSL=0 (Not used)
– 88 –
Pin Name
GTOP
XUGF
XPLCK
GFS
RFCK
C2PO
XRAOF
MNT3
MNT2
MNT1
MNT0
XTAI
XTAO
XTSL
DV
SS
FSTI
FSTO
FSOF
C16M
MD2
DOUT
EMPH
WFCK
SCOR
SBSO
EXCK
SUBQ
SQCK
MUTE
SENS
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
DV
DD
MIRR
DFCT
FOK
FSW
MON
NDP
MDS
LOCK
SSTP
SFDR
I/O
O
O
O
O
O
O
O
O
O
O
O
I
O
I
–
I
O
O
O
I
O
O
O
O
O
I
O
I
I
O
I
I
I
I
I
I
I
I
O
–
O
O
O
O
O
O
O
O
I
O
Function
DA 11 output when PSSL=1. GTOP output when PSSL=0 (Not used)
DA 10 output when PSSL=1. XUGF output when PSSL=0 (Not used)
DA 09 output when PSSL=1. XPLCK output when PSSL=0 (Not used)
DA 08 output when PSSL=1. GFS output when PSSL=0 (Not used)
DA 07 output when PSSL=1. RFCK output when PSSL=0
DA 06 output when PSSL=1. C2PO output when PSSL=0
DA 05 output when PSSL=1. XRA0F output when PSSL=0 (Not used)
DA 04 output when PSSL=1. MNT3 output when PSSL=0
DA 03 output when PSSL=1. MNT2 output when PSSL=0
DA 02 output when PSSL=1. MNT1 output when PSSL=0
DA 01 output when PSSL=1. MNT0 output when PSSL=0
X’tal oscillator circuit input
X’tal oscillator circuit output
X’tal selection input pin
Digital ground
2/3 divider input of pins 62, 63
2/3 divider output of pins 62, 63
(Not used)
16.9344 MHz output (Not used)
Digital-out ON/OFF control pin (+5V)
Digital-out output pin
Playback disc output in emphasis mode (Not used)
WFCK (Write Frame Clock) output
Sub-code sync output
Sub-P through Sub-W serial output (Not used)
Clock input for SBSO read-out
Sub-Q 80-bit output
Clock input for SQSO read-out
Muting selection pin
SENS output
System reset
Used in 1-track jump mode (+5V)
SENS serial data read-out clock
Defect selection pin (Ground)
Input pin for anti-shock (Ground)
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
Numbers of track counted signal output (Not used)
Digital power supply
Mirror signal output
Defect signal output (DFCT: Defect)
Focus OK output
Output to select spindle motor output filter (Not used)
Output to control ON/OFF of spindle motor (Not used)
Output to control spindle motor servo
Output to control spindle motor servo (Not used)
GFS (Guarded Frame Sync) is sampled by 460 Hz. H when GFS is H (Not used)
Input signal to detect disc inner most track
Sled drive output
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
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