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Model
MHC-S9D ST-S9
Pages
34
Size
3.72 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
mhc-s9d-st-s9.pdf
Date

Sony MHC-S9D / ST-S9 Service Manual ▷ View online

21
ST-S9
 DSP  BOARD  IC601  CXD9617R (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
Ground terminal
2
XRST
I
Reset signal input from the M61512FP (IC607)    “L”: reset
3
EXTIN
I
Master clock signal input terminal    Not used (fixed at “L”)
4
FS2
I
Sampling frequency selection signal input terminal    Not used (fixed at “L”)
5
VDDI
Power supply terminal (+2.6V)
6
FS1
I
Sampling frequency selection signal input terminal    Not used (fixed at “L”)
7
PLOCK
O
Internal PLL lock signal output terminal    Not used (open)
8
VSS
Ground terminal
9
MCLK1
I
Oscillation clock signal input from the digital audio interface receiver (IC604)
10
VDDI
Power supply terminal (+2.6V)
11
VSS
Ground terminal
12
MCLK2
O
Oscillation clock signal output terminal    Not used (open)
13
MS
I
Master/slave selection signal input terminal    “L”: slave, “H”: master (fixed at “L” in this set)
14
SCKOUT
O
Internal system clock signal output to the digital filter (IC606)
15
LRCKI1
I
L/R sampling clock signal (44.1 kHz) input terminal    Not used (open)
16
VDDE
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal (2.8224 MHz) input terminal    Not used (open)
18
SDI1
I
Audio serial data input from the D/A, A/D converter (IC605)
19
LRCKO
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter 
(IC606)
20
BCKO
O
Bit clock signal (2.8224 MHz) output to the D/A, A/D converter (IC605) and digital filter (IC606)
21
VSS
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver (IC604)
23 to 25
SDO1 to SDO3
O
Audio serial data output to the A/D, D/A converter (IC604)
26
SDO4
O
Audio serial data output to the digital filter (IC606)
27
SPDIF
O
S/PDIF signal output terminal    Not used (open)
28
LRCKI2
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver (IC604)
29
BCKI2
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver (IC604)
30
SDI2
I
Audio serial data input from the digital audio interface receiver (IC604)
31
VSS
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller (IC501)
33
HDIN
I
Write data input from the system controller (IC501)
34
HCLK
I
Clock signal input from the system controller (IC501)
35
HDOUT
O
Read data output to the system controller (IC501)
36
HCS
I
Chip select signal input from the system controller (IC501)
37
SDCLK
O
Clock signal output terminal    Not used (open)
38
CLKEN
O
Clock enable signal output terminal    Not used (open)
39
RAS
O
Row address strobe signal output terminal    Not used (open)
40
VDDI
Power supply terminal (+2.6V)
41
VSS
Ground terminal
42
CAS
O
Column address strobe signal output terminal    Not used (open)
43
DQM
O
Output terminal of data input/output mask    Not used (open)
44
CS0
O
Chip select signal output to the S-RAM (IC602)
45
WE0
O
Write enable signal output to the S-RAM (IC602)
46
VDDE
Power supply terminal (+3.3V)
47
WMD1
I
S-RAM wait mode setting terminal    Fixed at “H” in this set
22
ST-S9
Pin No.
Pin Name
I/O
Description
48
VSS
Ground terminal
49
WMD0
I
S-RAM wait mode setting terminal    Fixed at “L” in this set
50
PAGE2
O
Page selection signal output terminal    Not used (open)
51
VSS
Ground terminal
52, 53
PAGE1, PAGE0
O
Page selection signal output terminal    Not used (open)
54
BOOT
I
Boot mode control signal input terminal    Not used (fixed at “L”)
55
BTACT
O
Boot mode state display signal output terminal    Not used (open)
56
BST
I
Boot trap signal input from the M61512FP (IC607)
57
MOD1
I
PLL input frequency select terminal     “L”: 384fs, “H”: 256fs (fixed at “H” in this set)
58
MOD0
I
Mode setting terminal     “L”: single chip mode, “H”: use prohibition (fixed at “L” in this set)
59
EXLOCK
I
PLL lock error and data error flag input from the digital audio interface receiver (IC604)
60
VDDI
Power supply terminal (+2.6V)
61
VSS
Ground terminal
62, 63
A17, A16
O
Address signal output terminal    Not used (open)
64 to 66
A15 to A13
O
Address signal output to the S-RAM (IC602)
67
GP10
O
L/R sampling clock signal (44.1 kHz) output to the D/A, A/D converter (IC605) and digital filter 
(IC606)
68
DECODE
O
Decode signal output to the system controller (IC501)
69
AUDIO
I
Bit 1 input terminal of channel status from the digital audio interface receiver (IC604)
70
VDDI
Power supply terminal (+2.6V)
71
VSS
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM (IC602)
76
VDDE
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM (IC602)
81
VSS
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM (IC602)
86
TDO
O
Simple emulation data output terminal    Not used (open)
87
TMS
I
Simple emulation data input start/end detection signal input terminal    Not used (open)
88
XTRST
I
Simple emulation asychronous break input terminal    Not used (open)
89
TCK
I
Simple emulation clock signal input terminal    Not used (open)
90
TDI
I
Simple emulation data input terminal    Not used (open)
91
VSS
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM (IC602)
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM (IC602)
100
VDDI
Power supply terminal (+2.6V)
101
VSS
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM (IC602)
106
VDDE
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM (IC602)
109, 110
A2, A1
O
Address signal output to the S-RAM (IC602)
111
VSS
Ground terminal
112
A0
O
Address signal output to the S-RAM (IC602)
113
PM
I
PLL reset signal input from the M61512FP (IC607)    “L”: reset
114, 115
SDI3, SDI4
I
Audio serial data input terminal    Not used (fixed at “L”)
116
SYNC
I
Synchronous/asychronous selection signal input terminal
“L”: Synchronous, “H”: asynchronous (fixed at “H” in this set)
117 to 119
VSS
Ground terminal
120
VDDI
Power supply terminal (+2.6V)
23
ST-S9
 DSP  BOARD  IC604  LC89056W-E (DIGITAL AUDIO INTERFACE RECEIVER)
Pin No.
Pin Name
I/O
Description
1
DISEL
I
Selection terminal of data input terminal    Fixed at “L” in this set
2
DOUT
O
Digital data output to the optical transceiver (IC609)
3
DIN0
I
Digital data input from the optical receiver (IC952) (for DVP-S9)
4
DIN1
I
Digital data input from the optical receiver (IC951) (for external input)
5
DIN2
I
Digital data input terminal    Not used (fixed at “L”)
6
DGND
Ground terminal (digital system)
7
DVDD
Power supply terminal (+3.3V) (digital system)
8
R
I
VCO gain control input terminal
9
VIN
I
VCO free run frequency setting input terminal
10
LPF
O
PLL loop filter setting output terminal
11
AVDD
Power supply terminal (+3.3V) (analog system)
12
AGND
Ground terminal (analog system)
13
CKOUT
O
Audio clock signal output to the CXD9617R (IC601)
14
BCK
O
Bit clock signal (2.8224 MHz) output to the CXD9617R (IC601)
15
LRCK
O
L/R sampling clock signal (44.1 kHz) output to the CXD9617R (IC601)
16
DATAO
O
Audio serial data output to the CXD9617R (IC601)
17
XSTATE
O
Source clock switching monitor output to the system controller (IC501)
18
DGND
Ground terminal (digital system)
19
DVDD
Power supply terminal (+3.3V) (digital system)
20
XMCK
O
Oscillation clock signal output to the CXD9617R (IC601)
21
XOUT
O
System clock output terminal (13.5 MHz)
22
XIN
I
System clock input terminal (13.5 MHz)
23
EMPHA
O
Emphasis information of channel status output terminal    Not used (open)
24
AUDIO
O
Bit 1 output terminal of channel status to the CXD9617R (IC601)
25
CSFLAG
O
Top 40 bit renovation flag output terminal of channel status    Not used (open)
26 to 28
F0 to F2
O
Input frequency calculation result output terminal    Not used (open)
29
VF
O
Validity flag output terminal    Not used (open)
30
DVDD
Power supply terminal (+3.3V) (digital system)
31
DGND
Ground terminal (digital system)
32
ERR9P
O
Nine times continuance data transmission error flag output terminal    Not used (open)
33
BPSYNC
O
Non-PCM burst and preamble sync signal output terminal    Not used (open)
34
ERROR
O
PLL lock error and data error flag output to the system controller (IC501)
35
DO
O
Read data output to the system controller (IC501)
36
DI
I
Write data input from the system controller (IC501)
37
CE
I
Chip enable signal input from the system controller (IC501)
38
CL
I
Clock signal input from the system controller (IC501)
39
XSEL
I
Selection input terminal of vibrator frequency terminal    Fixed at “H” in this set
40
MODE0
I
Mode setting input terminal    Fixed at “H” in this set
41
MODE1
I
Mode setting input terminal    Fixed at “H” in this set
42
DGND
Ground terminal (digital system)
43
DVDD
Power supply terminal (+3.3V) (digital system)
44
DOSEL0
I
Output data format selection signal input terminal    Fixed at “L” in this set
45
DOSEL1
I
Output data format selection signal input terminal    Fixed at “L” in this set
46
CKSEL0
I
Output clock selection signal input terminal    Fixed at “L” in this set
47
CKSEL1
I
Output clock selection signal input terminal    Fixed at “L” in this set
48
XMODE
I
System reset signal input from the M61512FP (IC607)
24
ST-S9
 DSP  BOARD  IC605  AK4527 (A/D, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
1
SDOS
I
Audio serial data source selection signal input terminal
“L”: internal ADC output, “H”: DAUX input (fixed at “L” in this set)                                               
2
I2C
I
Serial control mode selection signal input terminal    “L”: 3-wire serial, “H”: I2C bus                      
3
SMUTE
I
Soft muting on/off signal input from the system controller (IC501)    “L”: muting on
4
BICK
I
Bit clock signal (2.8224 MHz) input from the CXD9617R (IC601)
5
LRCK
I
L/R sampling clock (44.1 kHz) signal input from the CXD9617R (IC601)
6 to 8
SDTI1 to SDIT3
I
Audio serial data input from the CXD9617R (IC601)
9
SDTO
O
Audio serial data output to the CXD9617R (IC601)
10
DAUX
I
Audio serial data input terminal    Not used (fixed at “L”)
11
DFS
I
Double speed sampling mode signal input terminal
“L”: normal speed, “H”: double speed (fixed at “L” in this set)
12
DEM1
I
De-emphasis signal input terminal    Fixed at “L” in this set
13
DEM0
I
De-emphasis signal input terminal    Fixed at “H” in this set
14
TVDD
Power supply terminal (+5V) (for output buffer )
15
DVDD
Power supply terminal (+5V) (digital system)
16
DVSS
Ground terminal (digital system)
17
PDN
I
Power down and reset signal input from the M61512FP (IC607)    “L”: power down and reset
18 to 20
ICKS2 to ICKS0
I
Input clock signal selection terminal    Fixed at “L” in this set
21, 22
CAD1, CAD0
I
Chip address signal input terminal    Not used (fixed at “L”)
23
LOUT3
O
Analog signal output for center to the M61512FP (IC607)
24
ROUT3
O
Analog signal output for sub woofer to the M61512FP (IC607)
25
LOUT2
O
Analog signal output for surround L-ch to the M61512FP (IC607)
26
ROUT2
O
Analog signal output for surround R-ch to the M61512FP (IC607)
27
LOUT1
O
Analog signal output for front L-ch to the M61512FP (IC607)
28
ROUT1
O
Analog signal output for front R-ch to the M61512FP (IC607)
29
LIN–
I
L-ch analog signal negative input from the M61512FP (IC607)
30
LIN+
I
L-ch analog signal positive input from the M61512FP (IC607)
31
RIN–
I
R-ch analog signal negative input from the M61512FP (IC607)
32
RIN+
I
R-ch analog signal positive input from the M61512FP (IC607)
33
DZF2
I
Zero input detection terminal     Not used (open)
34
VCOM
O
Common voltage output terminal                                                                                                         
Large external capacitor is used to reduce power supply noise
35
VREFH
I
Reference voltage (+5V) input terminal
36
AVDD
Power supply terminal (+5V) (analog system)
37
AVSS
Ground terminal (analog system)
38
DZF1
I
Zero input detection terminal     Not used (open)
39
MCLK
I
Master clock signal input from the CXD9617R (IC601)
40
P/S
I
Parallel/serial selection signal input terminal
“L”: serial control mode, “H”: parallel control mode (fixed at “H” in this set)
41
DIF0
I
Audio data interface format terminal    Fixed at “L” in this set
42
DIF1
I
Audio data interface format terminal    Fixed at “H” in this set
43, 44
LOOP0, LOOP1
I
Loop back mode setting terminal    Fixed at “L” in this set
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