Sony MDS-S50 (serv.man2) Service Manual ▷ View online
53
MDS-S50
Pin No.
Pin Name
I/O
Description
48
D1
I/O
49
D0
I/O
50
D2
I/O
51
D3
I/O
52
MVCI
I (S)
Digital in PLL oscillation input from the external VCO Not used (fixed at “L”)
53
ASYO
O
Playback EFM full-swing output terminal
54
ASYI
I (A)
Playback EFM asymmetry comparator voltage input terminal
55
AVDD
—
Power supply terminal (+3.3V) (analog system)
56
BIAS
I (A)
Playback EFM asymmetry circuit constant current input terminal
57
RFI
I (A)
Playback EFM RF signal input from the CXA2523AR (IC101)
58
AVSS
—
Ground terminal (analog system)
59
PCO
O (3)
Phase comparison output for master clock of the recording/playback EFM master PLL
60
FILI
I (A)
Filter input for master clock of the recording/playback master PLL
61
FILO
O (A)
Filter output for master clock of the recording/playback master PLL
62
CLTV
I (A)
Internal VCO control voltage input of the recording/playback master PLL
63
PEAK
I (A)
Light amount signal (RF/ABCD) peak hold input from the CXA2523AR (IC101)
64
BOTM
I (A)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523AR (IC101)
65
ABCD
I (A)
Light amount signal (ABCD) input from the CXA2523AR (IC101)
66
FE
I (A)
Focus error signal input from the CXA2523AR (IC101)
67
AUX1
I (A)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523AR (IC101)
68
VC
I (A)
Middle point voltage (+1.65V) input from the CXA2523AR (IC101)
69
ADIO
O (A)
Monitor output of the A/D converter input signal Not used (open)
70
AVDD
—
Power supply terminal (+3.3V) (analog system)
71
ADRT
I (A)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
72
ADRB
I (A)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
73
AVSS
—
Ground terminal (analog system)
74
SE
I (A)
Sled error signal input from the CXA2523AR (IC101)
75
TE
I (A)
Tracking error signal input from the CXA2523AR (IC101)
76
DCHG
I (A)
Connected to the +3.3V power supply
77
TEST4
I
Input terminal for the test Not used (fixed at “H”)
78
ADFG
I (S)
ADIP duplex FM signal (22.05 kHz
±
1 kHz) input from the CXA2523AR (IC101)
79
F0CNT
O
Filter f0 control signal output to the CXA2523AR (IC101)
80
XLRF
O
Serial data latch pulse signal output to the CXA2523AR (IC101)
81
CKRF
O
Serial data transfer clock signal output to the CXA2523AR (IC101)
82
DTRF
O
Writing serial data output to the CXA2523AR (IC101)
83
APCREF
O
Control signal output to the reference voltage generator circuit for the laser automatic power
control
control
84
TEST0
O
Input terminal for the test Not used (open)
85
TRDR
O
Tracking servo drive PWM signal (–) output to the BH6511FS (IC141)
86
TFDR
O
Tracking servo drive PWM signal (+) output to the BH6511FS (IC141)
87
DVDD
—
Power supply terminal (+3.3V) (digital system)
88
FFDR
O
Focus servo drive PWM signal (+) output to the BH6511FS (IC141)
89
FRDR
O
Focus servo drive PWM signal (–) output to the BH6511FS (IC141)
90
FS4
O
Clock signal (176.4 kHz) output terminal (X’tal system) Not used (open)
91
SRDR
O
Sled servo drive PWM signal (–) output to the BH6511FS (IC141)
92
SFDR
O
Sled servo drive PWM signal (+) output to the BH6511FS (IC141)
93
SPRD
O
Spindle servo drive PWM signal (–) output to the BH6511FS (IC141)
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Two-way data bus with the D-RAM (IC153)
54
MDS-S50
Pin No.
Pin Name
I/O
Description
94
SPFD
O
Spindle servo drive PWM signal (+) output to the BH6511FS (IC141)
95
FGIN
I (S)
96
TEST1
I
97
TEST2
I
98
TEST3
I
99
DVSS
—
Ground terminal (digital system)
100
EFMO
O
EFM signal output terminal when recording mode
* I (S) stands for schmitt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O.
Input terminal for the test (fixed at “L”)
55
MDS-S50
•
MAIN BOARD IC1 M30805MG-211GP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
FL-DATA
O
Serial data output to the fluorescent indicator tube/LED driver (IC761)
2
FL-CLK
O
Serial data transfer clock signal output to the fluorescent indicator tube/LED driver (IC761)
3
A1 IN
I
Sircs remote control signal input terminal of the CONTROL A1II Not used (fixed at “H”)
4
RMC
I
Remote control signal input from the remote control receiver (IC781)
5 to 7
NC
O
Not used (open)
8
MUTE
O
Audio line muting on/off control signal output “L”: line muting on, “H”: line muting off
9
RESET
O
Reset signal output to the A/D, D/A converter (IC500) “L”: reset
10
LATCH
O
Serial data latch pulse signal output to the A/D, D/A converter (IC500)
11
LD-LOW
O
Loading motor drive voltage control signal output for the loading motor driver (IC440)
“H” active
“H” active
12
LDIN
O
Motor control signal output to the loading motor driver (IC440) “L” active *1
13
LDOUT
O
Motor control signal output to the loading motor driver (IC440) “L” active *1
Laser modulation selection signal output to the HF module switch circuit
Stop: “L”, Playback power: “H”,
Recording power:
14
MOD
O
15
BYTE
I
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
16
CNVSS
—
Ground terminal
17
XCIN
I
Sub system clock input terminal (32.768 kHz) Not used (open)
18
XCOUT
O
Sub system clock output terminal (32.768 kHz) Not used (open)
19
RESET
I
System reset signal input from the regulator (IC400) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
20
XOUT
O
Main system clock output terminal (10 MHz)
21
VSS
—
Ground terminal
22
XIN
I
Main system clock input terminal (10 MHz)
23
VCC
—
Power supply terminal (+3.3V)
24
NMI
I
Non-maskable interrupt input terminal “L” active (fixed at “H” in this set)
25
DQSY
I
Digital In U-bit CD format subcode Q sync (SCOR) input from the CXD2662R (IC151)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
26
PDOWN
I
Power down detection signal input from the regulator (IC400)
“L”: power down, normally: “H”
“L”: power down, normally: “H”
27
SQSY
I
Subcode Q sync (SCOR) input from the CXD2662R (IC151)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
28
KEYBD-CLK
I
Serial data transfer clock signal input from the key board Not used (fixed at “H”)
29
LDON
O
Laser diode on/off control signal output to the automatic power control circuit “H”: laser on
30
LIMIT-IN
I
Detection signal input from the sled limit-in detect switch (S101)
The optical pick-up is inner position when “L”
The optical pick-up is inner position when “L”
31
A1 OUT
O
Sircs remote control signal output terminal of the CONTROL A1II Not used (open)
2 sec
0.5 sec
*1 Loading motor (M103) control
LOADING
EJECT
BRAKE
STOP
LDIN (pin qs)
“L”
“H”
“L”
“H”
LDOUT (pin qd)
“H”
“L”
“L”
“H”
Terminal
Mode
56
MDS-S50
Pin No.
Pin Name
I/O
Description
32
XINT
I
Interrupt status input from the CXD2662R (IC151)
33
BEEP
O
Beep sound drive signal output
Headphone muting on/off control signal output “L”: muting on, “H”: muting off
(Used for the except US and Canadian model)
Headphone muting on/off control signal output “L”: muting on, “H”: muting off
(Used for the except US and Canadian model)
34
LRCKI
O
L/R sampling clock signal (44.1 kHz) output to the CXD2662R (IC151)
35
WRPWR
O
Laser power selection signal output to the CXD2662R (IC151) and HF module switch circuit
“L”: playback mode, “H”: recording mode
“L”: playback mode, “H”: recording mode
36
I2CCLK
I/O
Serial data transfer clock signal input/output terminal for the IIC bus
37
I2CDAT
I/O
Serial data input/output terminal for the IIC bus
38
SWDT
O
Writing serial data signal output to the CXD2662R (IC151)
39
VCC
—
Power supply terminal (+3.3V)
40
SRDT
I
Reading serial data signal input from the CXD2662R (IC151)
41
VSS
—
Ground terminal
42
SCLK
O
Serial data transfer clock signal output to the CXD2662R (IC151)
43
REC-SW
I
Detection signal input from the recording position of over write head (HR901) detect switch
(S105) “L” recording mode
(S105) “L” recording mode
44
TX0 (CLIP)
O
Serial data output to the CXD2662R (IC151)
45
RX0 (CLIP)
I
Serial data input
46
CLK (CLIP)
O
Bit clock signal (2.8224 MHz) output to the CXD2662R (IC151)
47
DIG-RST
O
Reset signal output to the CXD2662R (IC151) and BH6511FS (IC141) “L”: reset
48
SENS
I
Internal status (SENSE) input from the CXD2662R (IC151)
49
PLAY-SW
I
Detection signal input from the playback position of over write head (HR901) detect switch
(S104) “L” playback mode
(S104) “L” playback mode
50
XLATCH
O
Serial data latch pulse signal output to the CXD2662R (IC151)
51
OUT-SW
I
Detection signal input from the loading-out detect switch (S103)
“L” at a load-out position, others: “H”
“L” at a load-out position, others: “H”
52
RDY
O
Not used (open)
53
ALE
O
Not used (open)
54
HOLD
O
Not used (open)
55
HLDA
O
Not used (open)
56
MNT2 (XBUSY)
I
Busy monitor signal input from the CXD2662R (IC151)
57
VSS
—
Ground terminal
58
MNT1 (SHOCK)
I
Track jump detection signal input from the CXD2662R (IC151)
59
VCC
—
Power supply terminal (+3.3V)
60
EEP-WP
O
Writing protect signal output to the EEPROM (IC195)
61
SDA
I/O
Two-way data bus with the EEPROM (IC195)
62
BCLK
O
Not used (open)
63
OE
O
Data reading strobe signal output to the flash memory “L” active Not used (open)
64
BHE
O
Not used (open)
65
WE
O
Writing enable signal output to the flash memory “L” active Not used (open)
66
SCL
O
Clock signal output to the EEPROM (IC195)
67
REFLECT SW
I
Detection signal input from the disc reflection rate detect switch (S102-1)
“L”: high reflection rate disc, “H”: low reflection rate disc
“L”: high reflection rate disc, “H”: low reflection rate disc
68
PROTECT SW
I
REC-proof claw detection signal input from the protect detect switch (S102-2)
“H”: write protect
“H”: write protect
69 to 71
CS0 to CS2
O
Chip select signal output to the flash memory “L” active Not used (open)
72, 73
A20, A19
O
Address signal output to the flash memory Not used (open)
74
VCC
—
Power supply terminal (+3.3V)
75
A18
O
Address signal output to the flash memory Not used (open)
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