Sony MDS-MX101 Service Manual ▷ View online
— 49 —
Pin No.
1
2
3
4 to 9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
I/O
I
I
O
I
I
O
I
—
I
O
I
I
I
I
I
O
I
I
—
I
O
I
O
O
I
I
O
O
O
O
O
O
O
I
I
O
I
I
O
I
O
I
O
Description
I-V converted RF signal I input from the optical pick-up block detector
I-V converted RF signal J input from the optical pick-up block detector
Middle point voltage (+1.65V) generation output terminal
Signal input from the optical pick-up detector (A to F)
Light amount monitor input terminal
Laser amplifier output terminal to the automatic power control circuit
Reference voltage input terminal for setting laser power
Ground terminal
Connected to the temperature sensor
Output terminal for a temperature sensor reference voltage
Writing serial data input from the CXD2652AR (IC121)
Serial clock signal input from the CXD2652AR (IC121)
Serial latch signal input from the CXD2652AR (IC121)
Standby signal input terminal “L”:standby (fixed at “H” in this set)
Center frequency control voitage input terminal of internal circuit (BPF22, BPF3T, EQ) input from the
CXD2652AR (IC121)
Reference voltage output terminal (Not used)
Center frequency setting terminal for the internal circuit (EQ)
Center frequency setting terminal for the internal circuit (BPF3T)
Power supply terminal (+3.3V)
Center frequency setting terminal for the internal circuit (BPF22)
Tracking error signal output to the CXD2652AR (IC121)
Connected to the external capacitor for low-pass filter of the sled error signal
Sled error signal output to the CXD2652AR (IC121)
FM signal output of the ADIP
Receives a ADIP FM signal in AC coupling
Connected to the external capacitor for ADIP AGC
ADIP duplex signal (22.05kHz
±
1kHz) output to the CXD2652AR (IC121)
Auxiliary signal (I
3
signal/temperature signal) output to the CXD2652AR (IC121)
Focus error signal output to the CXD2652AR (IC121)
Light amount signal (ABCD) output to the CXD2652AR (IC121)
Light amount signal (RF/ABCD) bottom hold output to the CXD2652AR (IC121)
Light amount signal (RF/ABCD) peak hold output to the CXD2652AR (IC121)
Playback EFM RF signal output to the CXD2652AR (IC121)
Connected to the external capacitor for RF auto gain control circuit
Receives a RF signal in AC coupling
User comparator output terminal (Not used)
User comparator input terminal (Not used) (fixed at “L”)
Connected to the external capacitor for cutting the low band of the ADIP amplifier
User operational amplifier output terminal (Not used)
User operational amplifier inversion input terminal (Not used) (fixed at “L”)
RF signal output terminal
Receives a MO RF signal in AC coupling
MO RF signal output terminal
Pin Name
I
J
VC
A to F
PD
APC
APCREF
GND
TEMPI
TEMPR
SWDT
SCLK
XLAT
XSTBY
F0CNT
VREF
EQADJ
3TADJ
VCC
WBLADJ
TE
CSLED
SE
ADFM
ADIN
ADAGC
ADFG
AUX
FE
ABCD
BOTM
PEAK
RF
RFAGC
AGCI
COMPO
COMPP
ADDC
OPO
OPN
RFO
MORFI
MORFO
6-12.
IC PIN FUNCTION
• BD BOARD IC101 CXA2523R (RF AMPLIFIER)
— 50 —
• BD BOARD IC121 CXD2652AR
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, EFM/ACIRC ENCODER/DECODER, SHOCK
PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER, 2M BIT D-RAM)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
I
I
O
I
—
—
I
O
I
O
O
O
O
—
O
O
O
O
O
O
O
O
O
O
O
Description
Focus OK signal output to the mechanism controller (IC100) “H” is output when focus is on
Track jump detection signal output to the mechanism controller (IC100)
Monitor 2 signal output to the mechanism controller (IC100)
Monitor 3 signal output to the mechanism controller (IC100)
Writing data signal input from the mechanism controller (IC100)
Serial clock signal input from the mechanism controller (IC100)
Serial latch signal input from the mechanism controller (IC100)
Reading data signal output to the mechanism controller (IC100)
Internal status (SENSE) output to the mechanism controller (IC100)
Reset signal input from the mechanism controller (IC100) “L”:reset
Subcode Q sync (SCOR) output to the mechanism controller (IC100)
“L” is output every 13.3 msec Almost all, :H: is output
Digital In U-bit CD format subcode Q sync (SCOR) output to the mechanism controller (IC100)
“L” is output every 13.3 msec Almost all, “H” is output
Laser power selection signal input from the mechanism controller (IC100)
“H”: recording mode, “L”: playback mode
Interrupt status output to the mechanism controller (IC100)
Recording data output enable signal input from the mechanism controller (IC100)
Writing data transmission timing input (Also serves as the magnetic head on/off output)
System clock signal (512Fs=22.5792 MHz) input from the A/D, D/A converter (IC202)
System clock signal (512Fs=22.5792 MHz) output terminal (Not used)
Input terminal for the system clock frequency setting
“L”:45.1584MHz, “H”:22.5792MHz (fixed at “H” in this set)
Test pin
Ground terminal (digital system)
Digital audio signal input terminal when recording mode (for optical in)
Digital audio signal output terminal when playback mode (for optical out)
Recording data input from the A/D, D/A converter (IC202)
Playback data output to the A/D, D/A converter (IC202)
L/R clock signal (44.1kHz) output to the A/D, D/A converter (IC202)
Bit clock signal (2.8224MHz) output to the A/D, D/A converter (IC202)
Clock signal (11.2896MHz) output terminal (Not used)
Power supply terminal (+3.3V) (digital system)
Address signal output to the external D-RAM
Pin Name
FOK
SHCK
XBUSY
SLOC
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
TEST G
RVSS
DIN
DOUT
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03
A02
A01
A00
A10
A04
A05
A06
A07
A08
A11
* I (A) for analog input, O (3) for 3-state output, I (S) for schmitt input, and O (A) for analog output in the column I/O.
— 51 —
Pin No.
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
I/O
—
O
O
O
O
O
I/O
I/O
I/O
I/O
I (S)
O
I (A)
—
I (A)
I (A)
—
O (3)
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
—
I (A)
I (A)
—
I (A)
I (A)
I (A)
I (A)
I (A)
I (S)
O
O
O
O
O
O
Description
Ground terminal (digital system)
Output enable signal output to the external D-RAM
Column address strobe signal output to the external D-RAM
Address signal output to the external D-RAM
Row address strobe signal output to the external D-RAM
Write enable signal output to the external D-RAM
Two-way data bus for the external D-RAM
Digital in PLL oscillation input from the external VCO (fixed at “L”)
Playback EFM full-swing output
Playback EFM asymmetry comparator voltage input
Power supply terminal (+3.3V) (analog system)
Playback EFM asymmetry circuit constant current input
Playback EFM RF signal
Ground terminal (analog system)
Phase comparison output for clock playback analog PLL of the playback EFM (Not used)
Phase comparison output for master clock of the recording/playback EFM master PLL
Filter input for master clock of the recording/playback master PLL
Filter output for master clock of the recording/playback master PLL
Internal VCO control voltage input of the recording/playback master PLL
Light amound signal (RF/ABCD) peak hold input from the CXA2523R (IC101)
Light amount signal (RF/ABCD) bottom hold input from the CXA2523R (IC101)
Light amount signal (ABCD) input from the CXA2523R (IC101)
Focus error signal (I
3
signal/temperature signal) input from the CXA2523R (IC101)
Auxiliary signal (I
3
signal/temperature signal) input from the CXA2523R (IC101)
Middle point voltage (+1.65V) input from the CXA2523R (IC101)
Monitor output of the A/D converter input signal (Not used)
Power supply terminal (+3.3V) (analog system)
A/D converter operational range upper limit voltage input terminal (fixed at “H” in this set)
A/D converter operational range lower limit voltage input terminal (fixed at “L” in this set)
Ground system (analog system)
Sled error signal input from the CXA2523R (IC101)
Tracking error signal input from the CXA2523R (IC101)
Auxiliary signal input terminal (fixed at “L”)
Connected to the +3.3V power supply
Error signal input for the laser automatic power control (fixed at “L”)
ADIP duplex FM signal (22.05kHz
±
1kHz) input from the CXA2523R (IC101)
Filter f0 control signal output to the CXA2523R (IC101)
Serial latch signal output to the CXA2523R (IC101)
Serial clock signal output to the CXA2523R (IC101)
Writing data output to the CXA2523R (IC101)
Control signal output to the reference voltage generator circuit for the laser automatic power control
PWM signal output for the laser automatic power control (Not used)
Pin Name
DVSS
XOE
XCAS
A09
XRAS
XWE
D1
D0
D2
D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PDO
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUXI
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
AUX2
DCHG
APC
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
LDDR
* EFM : Eight to Fourteen Modulation
PLL
: Phase Locked Loop
VCO : Voltage Controll Oscillator
— 52 —
Pin No.
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
O
O
—
O
O
O
O
O
O
O
I (S)
I
I
I
—
O
Description
Tracking servo drive PWM signal output terminal (–)
Tracking servo drive PWM signal output terminal (+)
Power supply terminal (+3.3V) (digital system)
Focus servo drive PWM signal output terminal (+)
Focus servo drive PWM signal output terminal (–)
Clock signal (176.4kHz) output terminal (X’tal system) (Not used)
Sled servo drive PWM signal output terminal (–)
Sled servo drive PWM signal output terminal (+)
Spindle servo drive PWM signal output terminal (–)
Spindle servo drive PWM signal output terminal (+)
Spindle CAV servo FG input
Input terminal for the test (fixed at “L”)
Ground terminal (digital system)
EFM signal output terminal when recording mode
Pin Name
TRDR
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FG IN
TEST1
TEST2
TEST3
DVSS
EFMO
* I (S) of I/O is the Schmitt input.
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