Sony MDS-JE770 Service Manual ▷ View online
53
MDS-JE770
MNT0 (FOK)
MNT1 (SHCK)
MNT2 (XBUSY)
MNT3 (SLOC)
SWDT
SCLK
XLAT
SRDT
SENS
XRST
SQSY
DQSY
RECP
XINT
TX
OSCI
OSCO
XTSL
DIN0
DIN1
DOUT
DADTI
LRCKI
XBCKI
ADDT
DADT
LRCK
XBCK
FS256
DVDD
A03 to A00
A10
A04 to A08
A11
DVSS
XOE
XCAS
A09
XRAS
XWE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 - 34
35
36 - 40
41
42
43
44
45
46
47
• IC151 CXD2662R Digital Signal Processor, Digital Servo Signal Processor (BD BOARD)
Desription
Pin No.
Pin Name
I/O
O
O
O
O
I
I (S)
I (S)
O (3)
O (3)
I (S)
O
O
I
O
O
I
O
I
I
I
O
I
I
I
I
O
—
O
O
I
O
O
O
O
—
O
O
O
O
O
Not used (open)
Track jump detection signal output to the system control
In the state of executire command signal output
Not used (open)
Writing data signal input from the system control
Serial clock signal input from the system control
Serial latch signal input from the system control
Reading data signal output to the system control
Internal status (SENSE) output to the system control
Reset signal input from the system control
“L”: Reset
Subcode Q sync (SCOR) output to the system control
“L” is output every 13.3 msec. Almost all, “H” is output
Digital In U-bit CD format or MD format subcode Q sync (SCOR) output to the system
control
Laser power switching input from the system control
“H”: Recording, “L”: Playback
Interrupt status output to the system control
Recording data output enable input from the system control
System clock input (512Fs=22.5792 MHz)
System clock output (512Fs=22.5792 MHz) (Not used)
System clock frequency setting
“L”: 45.1584 MHz, “H”: 22.5792 MHz (Fixed at “H”)
Digital audio input (Optical input)
Digital audio input (Optical input) (Not used)
Digital audio output (Optical output) (Not used)
Serial data input
LR clock input
“H” : Lch, “L” : R ch
Serial data clock input
Data input from the A/D converter
Data output to the D/A converter
LR clock output for the A/D and D/A converter (44.1 kHz)
Bit clock output to the A/D and D/A converter (2.8224 MHz)
11.2896 MHz clock output (Not used)
+3V power supply (Digital)
DRAM address output
DRAM address output (Not used)
DRAM address output
DRAM address output (Not used)
Ground (Digital)
Output enable output for DRAM
CAS signal output for DRAM
Address output for DRAM
RAS signal output for DRAM
Write enable signal output for DRAM
* I (S) stands for Schmidt input, I (A) for analog input, O (3) for 3-state output, and O (A) for analog output in the column I/O
54
MDS-JE770
Description
Pin No.
Pin Name
I/O
48
49
50, 51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
D1
D0
D2, D3
MVCI
ASYO
ASYI
AVDD
BIAS
RFI
AVSS
PCO
FILI
FILO
CLTV
PEAK
BOTM
ABCD
FE
AUX1
VC
ADIO
AVDD
ADRT
ADRB
AVSS
SE
TE
DCHG
TEST4
ADFG
F0CNT
XLRF
CKRF
DTRF
APCREF
TEST0
TRDR
Data input/output for DRAM
Clock input from an external VCO (Fixed at “L”)
Playback EFM duplex signal output
Playback EFM comparator slice level input
+3V power supply (Analog)
Playback EFM comparator bias current input
Playback EFM RF signal input
Ground (Analog)
Phase comparison output for the recording/playback EFM master PLL
Filter input for the recording/playback EFM master PLL
Filter output for the recording/playback EFM master PLL
Internal VCO control voltage input for the recording/playback EFM master PLL
Light amount signal peak hold input from the CXA2523AR
Light amount signal bottom hold input from the CXA2523AR
Light amount signal input from the CXA2523AR
Focus error signal input from the CXA2523AR
Auxiliary A/D input
Middle point voltage (+1.5V) input from the CXA2523AR
Monitor output of the A/D converter input signal (Not used)
+3V power supply (Analog)
A/D converter operational range upper limit voltage input (Fixed at “H”)
A/D converter operational range lower limit voltage input (Fixed at “L”)
Ground (Analog)
Sled error signal input from the CXA2523AR
Tracking error signal input from the CXA2523AR
Connected to +3V power supply
Test input (Fixed at “H”)
ADIP duplex FM signal input from the CXA2523AR (22.05
± 1 kHz)
Filter f
0
control output to the CXA2523AR
Control latch output to the CXA2523AR
Control clock output to the CXA2523AR
Control data output to the CXA2523AR
Reference PWM output for the laser APC
PWM output for the laser digital APC (Not used)
Tracking servo drive PWM output (–)
I/O
I/O
I/O
I (S)
O
I (A)
I
I (A)
I (A)
—
O (3)
I (A)
O (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
I (A)
O (A)
I
I (A)
I (A)
—
I (A)
I (A)
I (A)
I
I (S)
O
O
O
O
O
O
O
• Abbreviation
EFM: Eight to Fourteen Modulation
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
PLL : Phase Locked Loop
VCO: Voltage Controlled Oscillator
55
MDS-JE770
Description
Pin No.
Pin Name
I/O
86
87
88
89
90
91
92
93
94
95
96 - 98
99
100
TFDR
DVDD
FFDR
FRDR
FS4
SRDR
SFDR
SPRD
SPFD
FGIN
TEST1 to TEST3
DVSS
EFMO
O
I
O
O
O
O
O
O
O
I (S)
I
—
O
Tracking servo drive PWM output (+)
+3V power supply (Digital)
Focus servo drive PWM output (+)
Focus servo drive PWM output (–)
176.4 kHz clock signal output (X’tal) (Not used)
Sled servo drive PWM output (–)
Sled servo drive PWM output (+)
Spindle servo drive PWM output (–)
Spindle servo drive PWM output (+)
Test input (Fixed at “L”)
Ground (Digital)
EFM output when recording
• Abbreviation
EFM: Eight to Fourteen Modulation
56
MDS-JE770
1
FLDT
O
Serial data signal output to the display driver.
2
FLCK
O
Serial clock signal output to the display driver. L: Active
3
A1-IN
I
A1 Control input.
4
SIRCS
I
Remote control input.
5 - 7
NC
—
Not used.
8
BYTE
I
Data bus changed input. (Connected to ground.)
9
CNVSS
—
Ground.
10
XIN-T
I
Not used . (open)
11
XOUT-T
O
Not used . (open)
12
S.RST
I
System rest input. L : reset
13
XOUT
O
Main clock output. (10MHz)
14
GND
—
Ground.
15
XIN
I
Main clock input. (10MHz)
16
VCC
I
Power supply. (+3.3V)
17
NMI
I
Fixed at H.
18
DQSY
I
Digital In U-bit format or MD format subcode Q sync (SCOR) input to CXD2662R.
19
P.DOWN
I
Power down detection input. L: Power down
20
SQSY
I
Subcode Q (SCOR) sync input from CXD2662R.
21
KB.CLK
O
Keyboard clock output.
22
KB.DATA
I
Keyboard data output.
23
IIC BUSY
I
IIC busy signal input.
24
A1 OUT
O
A1 control signal output.
25
XINIT
I
Interrupt status input from CXD2662R.
26
*BEEP
O
Not used. (open)
27
LRCKI
O
Not used. (open)
28
IIC POWER
O
IIC start-up check.
29
IIC CLK
O
IIC serial clock output.
30
IIC DATA
I/O
IIC serial data input/output.
31
SWDT
O
Writing data signal output to CXD2662R and AK4524.
32
SRDT
I
Reading data signal input from CXD2662R.
33
SCLK
O
Clock signal output to CXD2662R and AK4524.
34
KB.CLK-CTRL
O
Keyboard clock ON/OFF signal output.
35
CLIP-TX
O
Not used. (open)
36
CLIP-RX
I
Not used. (open)
37
XBCK1
O
Not used. (open)
38
MUTE
O
Line out muting output. L: Mute
39
ADA.RESET
O
Reset signal output to the AK4524. L: Active
Description
Pin Name
Pin No.
I/O
• IC1 M30803MG-106FP SYSTEM CONTROL (MAIN BOARD)
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