Sony MDS-JE480 Service Manual ▷ View online
53
MDS-JE480
1
FLDT
O
Serial data output to the display driver
2
FLCK
O
Serial clock signal output to the display driver. L: Active
3
A1-IN
I
A1 Control input (Not used) (Open)
4
SIRCS
I
Remote control input
5 - 7
NC
—
Not used
8
BYTE
I
Data bus changed input (Fixed at “L”)
9
CNVSS
—
Ground
10
XIN-T
I
Not used (Open)
11
XOUT-T
O
Not used (Open)
12
S.RST
I
System rest input
13
XOUT
O
Main clock output (10MHz)
14
GND
—
Ground
15
XIN
I
Main clock input (10MHz)
16
VCC
—
Power supply
17
NMI
I
Fixed at H (Fixed at “H”)
18
DQSY
I
Digital in sync input (Record system)
19
P.DOWN
I
Power down detection input L: Power down
20
SQSY
I
ADIP (MO) sync or subcode Q (PIT) sync input from CXD2664R (Playback system)
21
(KB.CLK)
I
Keyboard clock input (Not used) (Open)
22
(KB.DATA)
I
Keyboard data input (Not used) (Open)
23
(IIC BUSY)
I
IIC cable connect check (Not used) (Open)
24
(A1 OUT)
O
A1 control output (Not used) (Open)
25
XINIT
I
Interrupt status input from CXD2664R
26
*BEEP
O
Not used (Open)
27
(LRCKI)
O
Not used (Open)
28
(IIC POWER)
O
Not used (Open)
29
(IIC CLK)
O
Not used (Open)
30
(IIC DATA)
I/O
Not used (Open)
31
SWDT
O
Writing data signal output to the serial bus
32
SRDT
I
Reading data signal input from the serial bus
33
SCLK
O
Clock signal output to the serial bus
34
(KB.CLK-CTRL)
O
Keyboard clock ON/OFF signal output (Not used) (Open)
35
(CLIP-TX)
O
Not used (Open)
36
(CLIP-RX)
I
Not used (Open)
37
(XBCK1)
O
Not used (Open)
38
MUTE
O
Line out muting output
39
ADA.RESET
O
Reset signal output to the AK4552
40
ADA. LATCH
O
Latch signal output to the AK4552 (Not used) (Open)
41
EPN
I
Not used (Fixed at L)
42
(L : DINT1/H : CLIP)
O
Not used (Open)
43
NC
O
Not used (Open)
44
PROTECT
I
Recording-protection claw detection input from the protection detection switch H: Protect
45
SCL
O
Clock signal output to the EEP-ROM
46
CE
O
Not used (Pull-up)
47
EEP-WP
O
EEP-ROM write protect signal output L: write possibility
48
XBUSY
I
In the state of executive command from the CXD2664R
Description
Pin Name
Pin No.
I/O
• IC1 M30622MGN-373FP SYSTEM CONTROL (MAIN BOARD)
54
MDS-JE480
Description
Pin Name
Pin No.
I/O
49
OUT-SW
I
Detection signal input from the loading out detection switch
50
XLATCH
O
Latch signal output to the serial bus
51
PLAY-SW
I
Detection signal input from the playback position detection switch L: PLAY
52
DIG-RST
O
Digital rest signal output to the CXD2664R and motor driver
53
REC-SW
I
Detection signal input from the recording position detection switch L: REC
54
WR PWR
O
Write power ON/OFF output
55
LIMIT-IN
I
Detection input from the limit switch L: Sled limit-In H: Sled limit-Out
56
MOD
O
Laser modulation switching signal output
57
LDON
O
Laser ON/OFF control output
58
SENS
I
Internal status (SENSE) input from the CXD2664R
59
SHCK
I
Track jump signal input from the CXD2664R
60
SDA
I/O
Serial data input/output pin with the EEP-ROM
61
REFLECT
I
Disk reflection rate detection input from the reflect detection switch. H: Disk with low reflection rate
62
VCC
—
Power supply
63
NC
O
Not used (Open)
64
GND
—
Ground
65
LOAD LO
O
Loading motor voltage control output
66
LOAD OUT
O
Loading motor control output H: eject
67
LOAD IN
O
Loading motor control output H: loading
68 - 71
MODEL SEL 0 - 3
O
Not used (Open)
72
EMF
O
Deemphasis control signal output to the AK4552
73 - 80
NC
O
Not used (Open)
81
STB
O
Strobe signal output to the power supply circuit H: Power supply ON: L: standby
82
BEEP SW
O
Not used (Open)
83
REC
O
Not used (Open)
84
FLCS
O
Chip select signal output to the MSM9202
85, 86
D.VOL0,1
O
Not used (Open)
87, 88
JOG0, JOG1
I
Jog dial pulse input from the rotary encoder
89
IOP
I
Optical Pick-up voltage (current) detect signal input
90
DISTINATION
I
Model discrimination
91
MODEL SEL
I
Model discrimination
92
TIMER
I
Not used (Open)
93
KEY3
I
Not used (Fixed at “H”)
94, 95
KEY2, 1
I
Key input pin (A/D input)
96
AVSS
—
Ground
97
KEY0
I
Key input pin (A/D input)
98
VREF
I
A/D reference voltage (Fixed at “H”)
99
AVCC
—
Power supply
100
NC
I
Not used (Fixed at “L”)
55
MDS-JE480
6-14. IC BLOCK DIAGRAMS
IC101 CXA2523AR (BD BOARD)
–1
–2
+
–
IVR
BB
+
–
IVR
AA
+
–
IVR
CC
+
–
IVR
DD
+
–
IVR
+
–
EE
EE'
EFB
TESW
PTGR
48
MORFO
47
MORFI
46
RFO
45
OPN
44
OPO
43
ADDC
42
COMPP
41
COMPO
40
AGCI
39
RF AGC
38
RF
37
PEAK
36 BOTM
35 ABCD
34 FE
33 AUX
32 ADFG
31 ADAGC
30 ADIN
29 ADFM
28 SE
27 CSLED
26 TE
25 WBLADJ
24
VCC
23
3TADJ
22
EQADJ
21
VREF
20
F0CNT
19
XSTBY
18
XLAT
17
SCLK
16
SWDT
15
TEMPR
14
TEMPI
13
GND
12
APCREF
11
APC
10
PD
9
F
8
E
7
D
6
C
5
B
4
A
3
VC
VI CONV
BGR
VREF
SCRI - PARA
DECODE
+ –
–
+
AUXSW
COMMAND
+
–
IVR
GSW
+
–
FF
FBAL
FF'
TG
SEA
–
+
–
+
–1
–2
TG
TEA
WBL
3T
EQ
–
–
+
+
+
+
–
–
–
–
–
–
DET
ADIP
AGC
WBL
BPF22
BPFC
ABCDA
FEA
WBL
ATA
–
+
CVB
+
–
RFA1
–
–
–
–
1
2
–
–
–
–
–
1
2
2
GRVA
OFST
RFA2
GRV
HLPT
PTGR
–2
–1
–1
–2
BOTTOM
PEAK
RF AGC
EQ
EQ
DET
P-P
WBL
3T
WBL
TEMP
PBH
–
+
USROP
+
–
USRC
3T
BPF3T
PEAK3T
1
I
2
J
RFA3
PBSW
AUX
SW
IV
ESW
EBAL
56
MDS-JE480
IC201 CXD2664R (BD BOARD)
115
114 113 112
111
110 109
EFMO
116
VDIO2
117
VSIO2
118
VDC4
119
VSC4
120
MDDT1
TST3
TST2
TST1
FGIN
SPFD
SPRD
108
SFDR
107
SRDR
106
FS4
105
FRDR
104
FFDR
103
TFDR
102
TRDR
101
LDDR
100
APCR
99
DTRF
98
CKRF
97
XLRF
94
F0CN
95
VDC3
96
VSC3
91
ADFG
93
VSIO1
92
VDIO1
86
87
88
89
90
TE
85 SE
AVS2
AVD2
APC
DCHG
DCHG
84 ADRB
83 ADRT
82 ADIO
75 CLTV
74 FILO
73 FILI
72 PCO
70 RFI
71 AVS1
69 BIAS
68 ASYI
67 ASYO
66 AVD1
65 TEST2
64 TEST1
63 TEST0
62 DRVSS1
61 DRVDD1
81 VC
80 AUX1
79 FE
78 ABCD
77 BOTM
76 PEAK
60
A03
59
A04
58
VSC2
57
VDC2
56
A02
55
A05
54
A01
53
A06
52
A00
51
A07
50
A10
49
A08
48
A09
47
XRAS
46
XCAS
45
D1
44
D2
43
D0
42
D3
41
A11
37
XWE
XOE
39
DRVDD0
40
DRVSS0
38
35
XBCK
36
FS256
33
DADT
34
LRCK
31
VSC1
32
ADDT
29
XBCKI
30
VDC1
28
LRCKI
27
DATAI
26
DOUT
25
DIN1
24
DIN0
23
XTSL
20
OSCO
21
OSCN
22
VSIO0
19
OSCI
18
VDIO0
17
TX
16
XINT
15
RPWR
14
DQSY
13
SQSY
12
XRST
11
SENS
10
SRDT
9
VSC0
8
XLAT
7
SCLK
6
SWDT
4
MNT3 (SLOC)
5
VDC0
3
MNT2 (XBUSY)
2
MNT1 (SHCK)
1
MNT0 (FOK)
PWM
GENERATOR
AUTO
SEQUENCER
SERVO
DSP
CPU I/F
MONITOR
CONTROL
CONTROL
SPINDLE
SERVO
EACH
BLOCK
BLOCK
EACH
BLOCK
BLOCK
DIGITAL
AUDIO
I/F
SAMPLING
RATE
CONVERTER
CLOCK
GENERATOR
SUBCODE
PROCESSOR
EACH
BLOCK
BLOCK
A/D
CONVERTER
ANALOG
MUX
EFM/ACIRC
ENCODER/
DECODER
PLL
SHOCK RESISTANT
MEMORY CONTROLLER
ATRAC/ATRAC3
ENCODER/DECODER
ADIP
DEMODULATOR/
DECODER
COMP
ADDRESS/DATA BUS A00 - A11, D0 - D3
IC401 BH6519FS-E2 (BD BOARD)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
VG
IN4R
IN4F
VM4
OUT4F
PGND4
OUT4R
VM34
OUT3R
PGND3
OUT3F
VM3
IN3F
IN3R
PSB
CAPA–
CAPA+
IN2R
IN2F
VM2
OUT2F
PGND2
OUT2R
VM12
OUT1R
PGND1
OUT1F
VM1
IN1F
IN1R
V
DD
CHARGE
PUMP.
OSC
INTERFACE
AMP
INTERFACE
AMP
AMP
INTERFACE
PREDRIVE
PREDRIVE
PREDRIVE
PREDRIVE
AMP
INTERFACE
AMP
AMP
AMP
V
DD
PSB
AMP
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