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ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
33
Pin No.
Pin Name
I/O
Description
M8
SDR_DATA13
I/O
Read/write data
M9
NAND_CEZ0
O
Chip enable
M10
GND
—
GND
M17
GND
—
GND
M18
GND
—
GND
M19
LCD_B0
O
B data (Not used (Open))
M22
LCD_G0
O
G data (Not used (Open))
M23
LCD_G1
O
G data (Not used (Open))
M24
LCD_G2
O
G data (Not used (Open))
M25
LCD_G3
O
G data (Not used (Open))
M26
VMIC
O
REGMIC power output terminal
N1
SDR_DATA12
I/O
Read/write data
N2
SDR_DATA11
I/O
Read/write data
N3
SDR_DATA10
I/O
Read/write data
N4
SDR_DATA9
I/O
Read/write data
N5
SDR_DATA8
I/O
Read/write data
N8
SDR_DATA7
I/O
Read/write data
N9
GND
—
GND
N10
GND
—
GND
N17
GND
—
GND
N18
GND
—
GND
N19
GND
—
GND
N22
LCD_G4
O
G data (Not used (Open))
N23
LCD_G5
O
G data (Not used (Open))
N24
LCD_R0
O
R data (Not used (Open))
N25
LCD_R1
O
R data (Not used (Open))
N26
VMICIN
I
REGMIC power input terminal
P1
SDR_DATA5
I/O
Read/write data
P2
SDR_DATA4
I/O
Read/write data
P3
SDR_DATA3
I/O
Read/write data
P4
SDR_DATA2
I/O
Read/write data
P5
SDR_DQM0
O
Write data mask
P8
SDR_DATA6
I/O
Read/write data
P9
GND
—
GND
P10
RESETZ
I
Reset input (Low active)
P17
GND
—
GND
P18
GND
—
GND
P19
GND
—
GND
P22
LCD_R3
O
R data (Not used (Open))
P23
LCD_PXCLK
O
Pixel clock (Not used (Open))
P24
ID
—
Not used (Open)
P25
I/O_A
—
Power supply to I/OA
P26
I/O_A
—
Power supply to I/OA
R1
SDR_DATA0
I/O
Read/write data
R2
SDR_DQM3
O
Write data mask (Not used (Open))
R3
SDR_DQM2
O
Write data mask (Not used (Open))
R4
SDR_DQM1
O
Write data mask
R5
SDR_WEZ
O
Write enable signal (Low active)
R8
SDR_DATA1
I/O
Read/write data
R9
GND
—
GND
R10
MWI_SI
I
Data input (Not used (Open))
R17
U70_CTSZ
I
connection/On destination/On device data send/receive ready (Low active) (Not used (Open))
R18
U70_RTSZ
O
Data send/receive ready (Low active) (Not used (Open))
R19
GND
—
GND
R22
LCD_R2
O
R data (Not used (Open))
R23
LCD_R4
O
R data (Not used (Open))
R24
GNDSINK
—
GND
R25
VDD_L0
—
Power supply to the logic block 0
R26
NC
—
Not used (Open)
T1
SDR_CKE0
O
Clock enable signal
ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
34
Pin No.
Pin Name
I/O
Description
T2
SDR_CSZ1
O
Chip select signal (Low active) (Not used (Open))
T3
SDR_CSZ0
O
Chip select signal (Low active)
T4
SDR_BA1
O
Bank address
T5
SDR_RASZ
O
RAS signal (Low active)
T8
SDR_CKE1
O
Clock enable signal (Not used (Open))
T9
GND
—
GND
T10
MWI_SO
O
Data output (Not used (Open))
T17
U70_SOUT
O
Serial data output
T18
U70_SRIN
I
Serial data input
T19
GND
—
GND
T22
LCD_R5
O
R data (Not used (Open))
T23
NC
—
Not used (Open)
T24
C_TMS
I
CPU debugger connection/On terminal
T25
VLOG
O
REGLOG power output terminal (1.86V)
T26
CKO
O
Crystal connection/On terminal
U1
SDR_A12
O
SDR address output
U2
SDR_A11
O
SDR address output
U3
SDR_A10
O
SDR address output
U4
SDR_A9
O
SDR address output
U5
SDR_A8
O
SDR address output
U8
SDR_CASZ
O
CAS signal (Low active)
U9
GND
—
GND
U10
MWI_CS0
O
Chip select 0 (Not used (Open))
U11
MWI_SK
O
Clock output (Not used (Open))
U12
GI/O_P1
I/O
General purpose input/output terminal 1 (Not used (Open))
U13
GI/O_P0
I/O
General purpose input/output terminal 0 (Not used (Open))
U14
L0_DET
I
Voltage monitor/reset of logic 0 block (Not used (Open))
U15
L1_DET
I
Voltage monitor of logic 1 block
U16
ERR_RST_REQZ
O
Not used (Open)
U17
CK32KI
I
Reference clock input 32.768 kHz (Not used (Open))
U18
REFCLKO
O
Reference clock output
U19
D_TCK
O
Input/output and interrupt input to general purpose I/O
U22
C_TDO
O
CPU debugger connection/On terminal
U23
VLOGIN
I
REGLOG power input terminal
U24
C_TCK
I
CPU debugger connection/On terminal
U25
VPLL
O
REGPLL power output terminal (1.2V)
U26
CKI
I
Crystal connection/On terminal
V1
I/O_A
—
Power supply to I/OA
V2
I/O_A
—
Power supply to I/OA
V3
I/O_A
—
Power supply to I/OA
V4
SDR_A6
O
SDR address output
V5
SDR_A5
O
SDR address output
V8
SDR_A7
O
SDR address output
V9
GND
—
GND
V10
SPI1_SK
O
SPI1 clock output
V11
MWI_CS1
O
Chip select 1 (Fixed to “L”)
V12
GND
—
GND
V13
GND
—
GND
V14
GND
—
GND
V15
GND
—
GND
V16
DSP_DET
I
Voltage monitor of DSP block
V17
D_TMS
O
CPU debugger connection/On terminal
V18
D_TDO
I
CPU debugger connection/On terminal (Not used (Open))
V19
D_TRSTZ
I
CPU debugger connection/On terminal (Not used (Open))
V22
C_RTCK
O
CPU debugger connection/On terminal
V23
C_TRSTZ
I
CPU debugger connection/On terminal (Low active)
V24
VPLLIN
I
REGPLL power input terminal
V25
VDSPIN
I
REGDSP power input terminal
V26
VDSP
O
REGDSP power output terminal (Not used (Open))
W1
I/OGND
—
GND
ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
35
Pin No.
Pin Name
I/O
Description
W2
GPI/O14
O
Input/output and interrupt input to general purpose I/O
W3
GPI/O15
O
Input/output and interrupt input to general purpose I/O
W4
SDR_A4
O
SDR address output
W5
SDR_A3
O
SDR address output
W8
SPI1_SO
O
SPI1 data output
W9
GND
—
GND
W10
SPI1_CS0
O
SPI1 Chip select 0
W11
GND
—
GND
W12
GND
—
GND
W13
GND
—
GND
W14
GND
—
GND
W15
GND
—
GND
W16
GND
—
GND
W17
GND
—
GND
W18
GND
—
GND
W19
EXTPCMCLK
I/O
External clock to audio/O block
W22
D_TDI
O
CPU debugger connection/On terminal
W23
C_TDI
O
CPU debugger connection/On terminal
W24
I/O_B
—
Power supply to I/OB
W25
I/O_B
—
Power supply to I/OB
W26
VL0
O
VDD-L2 power output terminal
Y1
I/OVDD
I
Power input terminal to internal I/O
Y2
GPI/O13
I/O
Input/output and interrupt input to general purpose I/O
Y3
GPI/O12
I/O
Input/output and interrupt input to general purpose I/O
Y4
SDR_A2
O
SDR address output
Y5
SDR_A1
O
SDR address output
Y22
TM1
I
Boot mode selectI/On (00: Ext-Bus,01: SD,10: NAND-Flash,11: MS)
Y23
TM0
I
CPU-ICE terminal functI/On selectI/On (0: CPU-ICE,1: DSP-ICE)
Y24
VDD_DSP
—
Power supply to DSP block
Y25
VDD_DSP
—
Power supply to DSP block
Y26
VHP
O
REGHP power output terminal (2.9V)
AA1
GPI/O11
O
Input/output and interrupt input to general purpose I/O
AA2
GPI/O10
O
Input/output and interrupt input to general purpose I/O
AA3
GPI/O9
I/O
Input/output and interrupt input to general purpose I/O
AA4
SDR_A0
O
SDR address output
AA5
SDR_CLK
O
Clock output
AA22
TMC2
I
Test terminal (Fixed to “L”)
AA23
TM4
I
Test terminal (Fixed to “L”)
AA24
TM2
I
Boot mode selectI/On (00: Ext-Bus,01: SD,10: NAND-Flash,11: MS)
AA25
VANAIN
I
REGANA power input terminal
AA26
VANA
O
REGANA power output terminal (2.85V)
AB1
VDD_L0
—
Power supply to the logic block 0
AB2
GPI/O8
I
Input/output and interrupt input to general purpose I/O
AB3
GPI/O7
I
Interrupt input to general purpose I/O
AB4
GPI/O6
O
Not used (Open)
AB5
SDR_BA0
O
Bank address
AB6
SPI0_CS1
O
SPI0 Chip select 1 (Fixed to “L”)
AB7
SPI0_SI
I
SPI0 data input (Not used (Open))
AB8
SPI1_SI
I/O
SPI1 data input (Not used (Open))
AB9
I/O_C
—
Power supply to I/OC
AB10
CAM_YUV7
I/O
YUV data input (Not used (Open))
AB11
CAM_YUV3
I/O
YUV data input (Not used (Open))
AB12
CAM_CLKI
I/O
Clock input (Not used (Open))
AB13
CAM_STR
I/O
Strobe ON/OFF (Not used (Open))
AB14
CAM_SCLK
I/O
Clock output (Not used (Open))
AB15
MS_DATA3
I/O
Data input/output (Not used (Open))
(To be used for both of Memory Stick and SD card)
AB16
MS_DATA2
I/O
Data input/output (Not used (Open))
(To be used for both of Memory Stick and SD card)
ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
36
Pin No.
Pin Name
I/O
Description
AB17
MS_DATA0
I
Data input/output (Not used (Open))
(To be used for both of Memory Stick and SD card)
AB18
MS_INSZ
I
SD insert detect/clock input(when SD is used) (Fixed to “L”)
(To be used for both of Memory Stick and SD card)
AB19
EXTCLK
I/O
External clock input for TIMER and PWM
AB20
PM1_SEN
O
PCM1 frame sync signal
AB21
PM1_CLK
O
PCM1 clock signal output
AB22
PM0_SEN
I/O
PCM0 frame sync signal (Default input)
AB23
TMC1
I
Test terminal (GND)
AB24
TM3
I
MODE (0: Master, 1: Copro) (Fixed to “L”)
AB25
GND1
—
GND
AB26
OSCIN
I
System clock input
AC1
I/O_A
—
Power supply to I/OA
AC2
I/O_A
—
Power supply to I/OA
AC3
I/O_A
—
Power supply to I/OA
AC4
GPI/O5
I/O
Input/output and interrupt input to general purpose I/O
AC5
GPI/O4
I
Input/output and interrupt input to general purpose I/O
AC6
SPI0_CS0
O
SPI0 Chip select 0
AC7
SPI0_SK
O
SPI0 clock output
AC8
SPI0_SO
O
SPI0 data output
AC9
I/O_C
—
Power supply to I/OC
AC10
CAM_YUV6
I/O
YUV data input (Not used (Open))
AC11
CAM_YUV2
I/O
YUV data input (Not used (Open))
AC12
CAM_VS
I/O
Vertical sync signal input (Not used (Open))
AC13
ISENSE
—
Not used (Open)
AC14
AVDD_LPLL
A/D converter PLL
AC15
AVDD_HPLL
A/D converter PLL
AC16
MS_DATA1
I/O
Data input/output (Not used (Open))
(To be used for both of Memory Stick and SD card)
AC17
MS_BS
I/O
Command response input/output (Not used (Open))
(To be used for both of Memory Stick and SD card)
AC18
MS_SCKO
O
Clock output (Not used (Open))
(To be used for both of Memory Stick and SD card)
AC19
IIC_SCL
I/O
Serial clock input/output (Not used (Open))
AC20
PM1_SO
O
PCM1 data output
AC21
PM0_CLK
I/O
PCM0 clock signal (Default input)
AC22
PM0_SO
O
PCM0 data output
AC23
PWM0
I/O
PWM interface signal
AC24
VL0IN
I
IOA power input terminal
AC25
I/O_C
—
Power supply to I/OC
AC26
OSCOUT
O
System clock output
AD1
NC
—
(Used to fi x solder ball to mount IC on board. Open)
AD2
GPI/O3
I
Input/output and interrupt input to general purpose I/O
AD3
GPI/O2
I
Input/output and interrupt input to general purpose I/O
AD4
GPI/O1
I
Input/output and interrupt input to general purpose I/O
AD5
GPI/O0
I
Input/output and interrupt input to general purpose I/O
AD6
ADINT
I
A/D converter interrupt output (Not used (Open))
AD7
SPI0_CS2
O
SPI0 Chip select 2
AD8
VDD_L1
—
Power supply to the logic block 1
AD9
I/O_C
—
Power supply to I/OC
AD10
CAM_YUV5
I/O
YUV data input (Not used (Open))
AD11
CAM_YUV1
I/O
YUV data input (Not used (Open))
AD12
CAM_HS
I/O
Horizontal sync input signal (Not used (Open))
AD13
TEST
I
Test terminal (Not used (Open))
AD14
AVDD_LPLL
I/O
A/D converter PLL
AD15
AVDD_HPLL
I/O
A/D converter PLL
AD16
OSENSE
—
Not used (Open)
AD17
BKBAT
I/O
Connected to RTC backup battery terminal
AD18
I/O_A
—
Power supply to I/OA
AD19
IIC_SDA
I/O
Serial data input/output (Not used (Open))
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