Sony ICD-SX57 / ICD-SX57DR9 / ICD-SX67 / ICD-SX67DR9 / ICD-SX77 Service Manual ▷ View online
ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
31
Pin No.
Pin Name
I/O
Description
E15
SWVBUS
O
Power supply logic output
E16
NC
—
Not used (Open)
E17
NC
—
Not used (Open)
E18
AB0_A4
I/O
Address output
E19
FLASHCLK
O
Clock for Nor-Flash (Not used (Open))
E20
AB0_A7
I/O
Address output (Not used (Open))
E21
AB0_A12
I/O
Address output (Not used (Open))
E22
AB0_CSZ1
I/O
Chip select output (Low active) (Not used (Open))
E23
AB0_A22
I/O
Address output (Not used (Open))
E24
AB0_A25
I/O
Address output
E25
AB0_D4
I/O
Data input/output
E26
ISENS
I
Not used (Open)
F1
DGND
—
GND
F2
CHGVBUS
I
Not used (Fixed to “L”)
F3
NC
—
Not used (Open)
F4
NC
—
Not used (Open)
F5
I/O_B
—
Power supply to I/OB
F22
AB0_CSZ2
I/O
Chip select output (Low active)
F23
AB0_A24
I/O
Address output
F24
AB0_D3
I/O
Data input/output
F25
AB0_D5
I/O
Data input/output
F26
VMONI
I
Battery voltage monitor terminal
G1
DVDD
I
Power input terminal for internal logic
G2
NC
—
Not used (Open)
G3
NC
—
Not used (Open)
G4
EXTRST
I
Reset input
G5
POWERSW
I
Power switch input
G22
AB0_CSZ3
O
Chip select output (Low active)
G23
AB0_D15
I/O
Data input/output
G24
AB0_D14
I/O
Data input/output
G25
AB0_D13
I/O
Data input/output
G26
CHGREGO
I/O
Battery charge control
H1
USBSUSPD
I
Not used (Fixed to “L”)
H2
PDSPDET
—
Not used (Open)
H3
SDR_DATA25
I/O
Read/write data
H4
SDR_DATA27
I/O
Read/write data (Not used (Open))
H5
SDR_DATA31
O
Read/write data output
H8
NAND_RBZ1
I/O
Ready BUSY output
H9
NAND_DA10
I/O
Address data input/output (Not used (Open))
H10
NAND_DA11
I/O
Address data input/output (Not used (Open))
H11
NAND_DA13
I/O
Address data input/output (Not used (Open))
H12
NAND_DA14
I/O
Address data input/output (Not used (Open))
H13
NAND_DA15
I/O
Address data input/output
H14
AB0_WAITZ
I/O
WAIT input (Not used (Open))
H15
AB0_ADVZ
I/O
Address enable (Not used (Open))
H16
AB0_WRZ
I/O
Write strobe output (Low active)
H17
AB0_CSZ0
I/O
Chip select output (Low active)
H18
AB0_A1
I/O
Address output
H19
AB0_A2
I/O
Address output
H22
AB0_D8
I/O
Data input/output
H23
AB0_D9
I/O
Data input/output
H24
AB0_D7
I/O
Data input/output
H25
AB0_D6
I/O
Data input/output
H26
CHGADP
I
Battery charge control input
J1
I/O_A
—
Power supply to I/OA
J2
I/O_A
—
Power supply to I/OA
J3
I/O_A
—
Power supply to I/OA
J4
SDR_DATA29
I/O
Read/write data (Not used (Open))
J5
SDR_DATA30
I/O
Read/write data
J8
NAND_RBZ2
I/O
Ready BUSY output
ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
32
Pin No.
Pin Name
I/O
Description
J9
NAND_DA9
I/O
Address data input/output (Not used (Open))
J10
NAND_DA12
I/O
Address data input/output (Not used (Open))
J11
GND
—
GND
J12
GND
—
GND
J13
GND
—
GND
J14
GND
—
GND
J15
GND
—
GND
J16
GND
—
GND
J17
GND
—
GND
J18
AB0_BENZ0
I/O
Byte enable output (Not used (Open))
J19
AB0_RDZ
I/O
Read strobe output (Low active)
J22
AB0_D10
I/O
Data input/output
J23
AB0_D11
I/O
Data input/output
J24
AB0_D12
I/O
Data input/output
J25
CHGGND1
—
GND
J26
CVPHC
I
Battery charge control
K1
VDD_L1
—
Power supply to the logic block 1
K2
VDD_L1
—
Power supply to the logic block 1
K3
VDD_L1
—
Power supply to the logic block 1
K4
SDR_DATA28
I/O
Read/write data (Not used (Open))
K5
SDR_DATA26
I/O
Read/write data (Not used (Open))
K8
NAND_RBZ3
I/O
Ready BUSY output
K9
NAND_DA6
I/O
Address data input/output
K10
GND
—
GND
K11
GND
—
GND
K12
GND
—
GND
K13
GND
—
GND
K14
GND
—
GND
K15
GND
—
GND
K16
GND
—
GND
K17
GND
—
GND
K18
GND
—
GND
K19
AB0_BENZ1
I/O
Byte enable output (Not used (Open))
K22
LCD_HSYNC
O
Horizontal sync output signal (Not used (Open))
K23
LCD_ENABLE
O
Data enable (Not used (Open))
K24
LCD_VSYNC
O
Vertical sync output signal (Not used (Open))
K25
CHGGND2
—
GND
K26
CHG
O
Battery charge control output
L1
SDR_DATA23
I/O
Read/write data (Not used (Open))
L2
SDR_DATA22
I/O
Read/write data (Not used (Open))
L3
SDR_DATA21
I/O
Read/write data (Not used (Open))
L4
SDR_DATA20
I/O
Read/write data (Not used (Open))
L5
SDR_DATA24
I/O
Read/write data (Not used (Open))
L8
SDR_DATA19
I/O
Read/write data (Not used (Open))
L9
NAND_DA4
I/O
Address data input/output
L10
GND
—
GND
L11
NC
—
Not used (Open)
L17
GND
—
GND
L18
GND
—
GND
L19
LCD_B1
O
B data (Not used (Open))
L22
LCD_B2
O
B data (Not used (Open))
L23
LCD_B3
O
B data (Not used (Open))
L24
LCD_B4
O
B data (Not used (Open))
L25
LCD_B5
O
B data (Not used (Open))
L26
BSEN
I
Battery voltage detection/On input (Fixed to “L”)
M1
SDR_DATA18
I/O
Read/write data (Not used (Open))
M2
SDR_DATA17
I/O
Read/write data (Not used (Open))
M3
SDR_DATA16
I/O
Read/write data (Not used (Open))
M4
SDR_DATA15
I/O
Read/write data
M5
SDR_DATA14
I/O
Read/write data
ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
33
Pin No.
Pin Name
I/O
Description
M8
SDR_DATA13
I/O
Read/write data
M9
NAND_CEZ0
O
Chip enable
M10
GND
—
GND
M17
GND
—
GND
M18
GND
—
GND
M19
LCD_B0
O
B data (Not used (Open))
M22
LCD_G0
O
G data (Not used (Open))
M23
LCD_G1
O
G data (Not used (Open))
M24
LCD_G2
O
G data (Not used (Open))
M25
LCD_G3
O
G data (Not used (Open))
M26
VMIC
O
REGMIC power output terminal
N1
SDR_DATA12
I/O
Read/write data
N2
SDR_DATA11
I/O
Read/write data
N3
SDR_DATA10
I/O
Read/write data
N4
SDR_DATA9
I/O
Read/write data
N5
SDR_DATA8
I/O
Read/write data
N8
SDR_DATA7
I/O
Read/write data
N9
GND
—
GND
N10
GND
—
GND
N17
GND
—
GND
N18
GND
—
GND
N19
GND
—
GND
N22
LCD_G4
O
G data (Not used (Open))
N23
LCD_G5
O
G data (Not used (Open))
N24
LCD_R0
O
R data (Not used (Open))
N25
LCD_R1
O
R data (Not used (Open))
N26
VMICIN
I
REGMIC power input terminal
P1
SDR_DATA5
I/O
Read/write data
P2
SDR_DATA4
I/O
Read/write data
P3
SDR_DATA3
I/O
Read/write data
P4
SDR_DATA2
I/O
Read/write data
P5
SDR_DQM0
O
Write data mask
P8
SDR_DATA6
I/O
Read/write data
P9
GND
—
GND
P10
RESETZ
I
Reset input (Low active)
P17
GND
—
GND
P18
GND
—
GND
P19
GND
—
GND
P22
LCD_R3
O
R data (Not used (Open))
P23
LCD_PXCLK
O
Pixel clock (Not used (Open))
P24
ID
—
Not used (Open)
P25
I/O_A
—
Power supply to I/OA
P26
I/O_A
—
Power supply to I/OA
R1
SDR_DATA0
I/O
Read/write data
R2
SDR_DQM3
O
Write data mask (Not used (Open))
R3
SDR_DQM2
O
Write data mask (Not used (Open))
R4
SDR_DQM1
O
Write data mask
R5
SDR_WEZ
O
Write enable signal (Low active)
R8
SDR_DATA1
I/O
Read/write data
R9
GND
—
GND
R10
MWI_SI
I
Data input (Not used (Open))
R17
U70_CTSZ
I
connection/On destination/On device data send/receive ready (Low active) (Not used (Open))
R18
U70_RTSZ
O
Data send/receive ready (Low active) (Not used (Open))
R19
GND
—
GND
R22
LCD_R2
O
R data (Not used (Open))
R23
LCD_R4
O
R data (Not used (Open))
R24
GNDSINK
—
GND
R25
VDD_L0
—
Power supply to the logic block 0
R26
NC
—
Not used (Open)
T1
SDR_CKE0
O
Clock enable signal
ICD-SX57/SX57DR9/SX67/SX67DR9/SX77
34
Pin No.
Pin Name
I/O
Description
T2
SDR_CSZ1
O
Chip select signal (Low active) (Not used (Open))
T3
SDR_CSZ0
O
Chip select signal (Low active)
T4
SDR_BA1
O
Bank address
T5
SDR_RASZ
O
RAS signal (Low active)
T8
SDR_CKE1
O
Clock enable signal (Not used (Open))
T9
GND
—
GND
T10
MWI_SO
O
Data output (Not used (Open))
T17
U70_SOUT
O
Serial data output
T18
U70_SRIN
I
Serial data input
T19
GND
—
GND
T22
LCD_R5
O
R data (Not used (Open))
T23
NC
—
Not used (Open)
T24
C_TMS
I
CPU debugger connection/On terminal
T25
VLOG
O
REGLOG power output terminal (1.86V)
T26
CKO
O
Crystal connection/On terminal
U1
SDR_A12
O
SDR address output
U2
SDR_A11
O
SDR address output
U3
SDR_A10
O
SDR address output
U4
SDR_A9
O
SDR address output
U5
SDR_A8
O
SDR address output
U8
SDR_CASZ
O
CAS signal (Low active)
U9
GND
—
GND
U10
MWI_CS0
O
Chip select 0 (Not used (Open))
U11
MWI_SK
O
Clock output (Not used (Open))
U12
GI/O_P1
I/O
General purpose input/output terminal 1 (Not used (Open))
U13
GI/O_P0
I/O
General purpose input/output terminal 0 (Not used (Open))
U14
L0_DET
I
Voltage monitor/reset of logic 0 block (Not used (Open))
U15
L1_DET
I
Voltage monitor of logic 1 block
U16
ERR_RST_REQZ
O
Not used (Open)
U17
CK32KI
I
Reference clock input 32.768 kHz (Not used (Open))
U18
REFCLKO
O
Reference clock output
U19
D_TCK
O
Input/output and interrupt input to general purpose I/O
U22
C_TDO
O
CPU debugger connection/On terminal
U23
VLOGIN
I
REGLOG power input terminal
U24
C_TCK
I
CPU debugger connection/On terminal
U25
VPLL
O
REGPLL power output terminal (1.2V)
U26
CKI
I
Crystal connection/On terminal
V1
I/O_A
—
Power supply to I/OA
V2
I/O_A
—
Power supply to I/OA
V3
I/O_A
—
Power supply to I/OA
V4
SDR_A6
O
SDR address output
V5
SDR_A5
O
SDR address output
V8
SDR_A7
O
SDR address output
V9
GND
—
GND
V10
SPI1_SK
O
SPI1 clock output
V11
MWI_CS1
O
Chip select 1 (Fixed to “L”)
V12
GND
—
GND
V13
GND
—
GND
V14
GND
—
GND
V15
GND
—
GND
V16
DSP_DET
I
Voltage monitor of DSP block
V17
D_TMS
O
CPU debugger connection/On terminal
V18
D_TDO
I
CPU debugger connection/On terminal (Not used (Open))
V19
D_TRSTZ
I
CPU debugger connection/On terminal (Not used (Open))
V22
C_RTCK
O
CPU debugger connection/On terminal
V23
C_TRSTZ
I
CPU debugger connection/On terminal (Low active)
V24
VPLLIN
I
REGPLL power input terminal
V25
VDSPIN
I
REGDSP power input terminal
V26
VDSP
O
REGDSP power output terminal (Not used (Open))
W1
I/OGND
—
GND
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