Sony ICD-ST25 Service Manual ▷ View online
29
ICD-ST25
4-11. IC PIN FUNCTION DESCRIPTIONS
• IC6001 uPD77213F1-101-DA2 (DSP) (MAIN BOARD)
Pin No.
1 to 3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41 to 44
45
46
47
48
49
50
51
52
53
54
55
56
57
I/O
—
—
O
I/O
I
O
O
—
O
O
O
—
—
—
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
—
—
I
I
I
I
I
O
O
O
O
—
—
I/O
—
I
I
I/O
O
I
I
—
I
O
O
I
—
O
Description
Not used
I/O power supply (3.1V)
AD/DA chip select (Not used) (fixed at “L”)
AD/DA clock (Not used) (fixed at “L”)
AD/DA data input (Not used) (fixed at “L”)
AD/DA data output (Not used) (fixed at “L”)
Microphone power supply control (Not used) (fixed at “L”)
Ground terminal
Boot flash ROM write protect
Boot flash ROM chip select
Micropone sensitivity select (H: Conference, L: Dictation) (Not used) (fixed at “L”)
Ground terminal
Not used
I/O power supply (3.1 V)
Host data bus (Not used)
Host data bus (Not used)
Host data bus (Not used)
Host data bus (Not used)
Host data bus (Not used)
Host data bus (Not used)
Ground terminal
Core power supply (1.6 V)
Host data bus (Not used)
Host data bus (Not used)
Ground terminal
I/O power supply (3.1 V)
Host chip select (Pull-up) (fixed at “H”)
Host data access 1 (Pull-down) (fixed at “L”)
Host write (Pull-up) (fixed at “H”)
Host data access 0 (Pull-down) (fixed at “L”)
Host read (Pull-up) (fixed at “H”)
Not used
Serial data output
Host write enable (Not used)
Host read enable (Not used)
Ground terminal
I/O power supply (3.1 V)
Bit clock
Not used
ADA serial data input
Master clock
Clock for L-ch and R-ch (H: L-ch, L: R-ch)
Time sharing serial data output
Time sharing serial clock input
Time sharing serial output enable
Ground terminal
Time sharing serial data input
Time sharing serial input response (Not used)
Time sharing serial output request (Note used)
Time sharing serial input enable
I/O power supply (3.1 V)
Memory address bus 1 (Not used)
Pin Name
NC
EVDD
XADACS
ADACCLK
ADACDTI
ADACDTO
MICPWR
GND
XFMWP
XFMCS
MICSENSE
GND
NC
EVDD
HD1
HD2
HD0
HD3
HD5
HD4
GND
IVDD
HD7
HD6
GND
EVDD
XHCS
HA1
XHWR
HA0
XHRD
TIMOUT
SO
XHWE
XHRE
GND
EVDD
BCLK
NC
ADASI
MCLK
LRCLK
TSO
TSCK
TSOEN
GND
TSI
TSIAK
TSORQ
TSIEN
EVDD
MA1
30
ICD-ST25
Pin No.
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81 to 84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Pin Name
MA0
GND
IVDD
MA2
MA4
GND
MA3
MA7
MA5
MA8
MA6
MA9
MA10
GND
EVDD
MA11
MA12
MA14
MA13
MA16
MA15
EVDD
MA17
NC
EVDD
MA18
MA19
XMHOLDAK
XMRD
XMHOLDRQ
GND
EVDD
XMWAIT
XMWR
GND
IVDD
XMBSTB
MD0
GND
MD3
MD1
MD4
MD5
MD6
MD2
MD8
GND
EVDD
MD7
MD13
MD10
MD11
I/O
O
—
—
O
O
—
O
O
O
O
O
O
O
—
—
O
O
O
O
O
O
—
O
—
—
O
O
O
O
I
—
—
I
O
—
—
O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
—
I/O
I/O
I/O
I/O
Description
Memory address bus 0 (Not used)
Ground terminal
Core power supply (1.6 V)
Memory address bus 2 (Not used)
Memory address bus 4 (Not used)
Ground terminal
Memory address bus 3 (Not used)
Memory address bus 7 (Not used)
Memory address bus 5 (Not used)
Memory address bus 8 (Not used)
Memory address bus 6 (Not used)
Memory address bus 9 (Not used)
Memory address 10 (Not used)
Ground terminal
I/O power supply (3.1 V)
Memory address 11 (Not used)
Memory address 12 (Not used)
Memory address 14 (Not used)
Memory address 13 (Not used)
Memory address 16 (Not used)
Memory address 15 (Not used)
I/O power supply (3.1 V)
Memory address 17 (Not used)
Not used
I/O power supply (3.1 V)
Memory address 18 (Not used)
Memory address 19 (Not used)
Memory bus hold response (Not used)
Memory read-out (Not used)
Memory bus hold request (Pull-up) (fixed at “H”)
Ground terminal
I/O power supply (3.1 V)
Memory access weight (Pull-up)
Memory write (Not used)
Ground terminal
Core power supply (1.6 V)
Memory bus strobe (Not used)
Memory data bus (Not used)
Ground terminal
Memory data bus (Not used)
Memory data bus (Not used)
Memory data bus (Not used)
Memory data bus (Not used)
Memory data bus (Not used)
Memory data bus (Not used)
Memory data bus (Not used)
Ground terminal
I/O power supply (3.1 V)
Memory data bus (Not used)
Memory data bus (Not used)
Memory data bus (Not used)
Memory data bus (Not used)
31
ICD-ST25
Pin No.
113
114
115
116
117
118
119
120
121
122
123 to 126
127
128
129
130
131
132
133
134
135
136, 137
138
139
140
141
142
143
144, 145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161 to 164
Pin Name
MD9
MD14
GND
MD15
MD12
TICE
TMS
EVDD
GND
TDO
NC
XTRST
TCK
EVDD
IC
TDI
STOPS
CSTOP
IC
GND
PLL0,PLL1
XRST
GND
IVDD
PLL3
HALTS
GND
IVDD
PLL2
GND
EVDD
CLKOUT
CLKIN
BOOT1
GND
BOOT3
BOOT0
GND
BOOT2
FMSCK
TSIOEN
REQ
FMSDIO
NC
I/O
I/O
I/O
—
I/O
I/O
O
I
—
—
O
—
I
I
—
—
I
O
I
—
—
I
I
—
—
I
O
—
—
I
—
—
O
I
I
—
I
I
—
I
I/O
I
O
I/O
—
Description
Memory data bus (Not used)
Memory data bus (Not used)
Ground terminal
Memory data bus (Not used)
Memory data bus (Not used)
Test ICE
Test mode selection
I/O power supply (3.1 V)
Ground terminal
Test data output
Not used
Test reset
Test clock input
I/O power supply (3.1 V)
Internal connection (Not used)
Test data input
Stop (Open)
Clear stop mode (Pull-down) (fixed at “L”)
Internal connection (Not used)
Ground terminal
PLL rate setting 0 and 1
Reset
Ground terminal
Core power supply (1.6 V)
PLL rate setting 3
HALT
Ground terminal
Core power supply (1.6 V)
PLL rate setting 2
Ground terminal
I/O power supply (3.1 V)
Clock output
Clock input
Boot mode 1 (fixed at “H”)
Ground terminal
Boot mode 3 (fixed at “H”)
Boot mode 0 (fixed at “L”)
Ground terminal
Boot mode 2 (fixed at “H”)
Boot flash ROM serial clock
SIO enable
Request
Boot flash ROM serial data
Not used
32
ICD-ST25
• IC7003 MB91F233 (CPU) (MAIN BOARD)
Pin No.
1
2
3 to 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24 to 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49 to 74
75
76
77 to 82
83 to 86
87
88
89
90
91 to 94
95
96
97
98
99
100
101
I/O
O
O
I/O
O
O
I
—
—
—
—
O
O
O
O
I
O
O
O
O
O
O
O
—
—
—
I
I
I
I
—
I
I
I
—
—
O
—
—
O
O
I
I
I
I
—
I
O
O
I
O
O
O
Description
Serial clock output for DSP
Command latch enable signal output for FLASH
Data input/output to FLASH and USB
Chip enable signal output for FLASH
System clock control signal output for DSP
32KHz vibration terminal (input)
32KHz vibration terminal (input)
Internal logic backup voltage terminal
Ground terminal
Internal logic voltage terminal
Beep output
Write enable signal output for FLASH
Read enable signal output for FLASH
Address latch enable signal output for FLASH
Ready/Busy signal input from FLASH
Write protect signal output to FLASH
Address signal output to USB control
Chip select signal output to USB control
Read strobe signal output to USB control
Reset signal output to USB control
Low write strobe signal output to USB control
Chip enable signal output for FLASH (Not used)
Analog power supply
Reference voltage terminal
Ground (Analog) terminal
Battery voltage detect signal input
Key 0 A/D input
Key 1 A/D input
Directivity microphone switch signal input
Not used
DPC switch signal input
External microphone detect signal input
Headphone detect signal input
Ground terminal
Voltage terminal
LCD segment output terminal
Voltage terminal
Ground terminal
LCD segment output terminal
LCD common output terminal
Mode input terminal
Mode input terminal (fixed at “L”)
Mode input terminal (fixed at “L”)
CPU external reset signal input
LCD reference voltage terminal
FLASH overwrite RX
FLASH overwrite TX
FLASH power supply control signal output (L:ON)
Serial data input from RTC
Serial data output to RTC, ADC and DAC
Serial clock output to RTC, ADC and DAC
Chip select signal output to RTC
Pin Name
DSPSCK
FLMCLE
DATA0 to 7
XFLMCS0
DSPSYSCK
X0A32k
X1A32k
VCC3BCK
VSS
VCC3LGC
BEEP
XFLMWE
XFLMRE
XFLMALE
FLMRB
XFLMWP
USBADR0 to 6
XUSBCS
XUSBRD
XUSBRST
XUSBLWR
XFLMCS1
AVCC
AVREF
AVSS
BATT
KEYIN0
KEYIN1
MICSEL
NC
VUPDPC
XMICJACK
HPJACK
VSS
AVCC3IO
SEG0 to 25
DVCC
DVSS
SEG26 to 31
COM0 to 3
MOD2
MOD1
MOD0
XCPURST
LCDV0 to 3
RX
TX
XFLMPWR
AUSIN
AUSOT
AUSCK
RTCCS
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