Sony ICD-MS1 Service Manual ▷ View online
– 39 –
5-7.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC722 HD64F7198RVBP16 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
XEPCS
O
Chip select signal output to the EEPROM (IC723) “L” active
2
XLCDCS
O
Chip select signal output to the liquid crystal display module (LCD720) “L” active
3
VCC
—
Power supply terminal (+3.3V)
4
PA23
O
Not used (open)
5
SRCS
O
Chip enable signal output to the static RAM (IC727) “L” active
6
PA21
O
Not used (open)
7
PA20
O
Not used (open)
8
VSS
—
Ground terminal
9
MSINS
I
Memory stick insert detection signal input terminal
“L”: memory stick in, “H”: memory stick out
“L”: memory stick in, “H”: memory stick out
10
XRD
O
Output enable signal output to the static RAM (IC727) “L” active
11
MSBS
O
Serial bus state signal output to the memory stick
12
MSDIO
I/O
Serial data input/output with the memory stick
13
MSCLK
O
Serial clock signal output to the memory stick
14
XUB
O
Data bite control signal output to the static RAM (IC727) “L” active
15
XLB
O
Data bite control signal output to the static RAM (IC727) “L” active
16
XWAIT
I
Not used (open)
17
RTCCE
O
Chip enable signal output to the real time clock (IC721) “H” active
18
PA4
O
Not used (open)
19
PA0
O
Not used (open)
20
DSPTX
O
Playback serial data output to the ADPCM (IC164)
21
DSPRX
I
Recording serial data input from the ADPCM (IC164)
22
VCC
—
Power supply terminal (+3.3V)
23
VSS
—
Ground terminal
24
LCDDO
O
Serial data output to the liquid crystal display module (LCD720)
25
LCDDI
I
Serial data input from the liquid crystal display module (LCD720)
26
VSS
—
Ground terminal
27
VCC
—
Power supply terminal (+3.3V)
28
PB17
O
Not used (open)
29
PB16
O
Not used (open)
30
RDWR
O
Read/write data output to the static RAM (IC727) “L”: write data , “H”: read data
31
WAKEMSK2
O
X (R) sync control signal output terminal
32
WAKEMSK
O
X (R) sync control signal output terminal
33
VSS
—
Ground terminal
34
KEYCTL3
O
Key send signal output to the key matrix Not used (open)
35 to 37
KEYCTL2 to
KEYCTL0
O
Key send signal output to the key matrix
38
MICPOW
O
Power supply on/off control signal output to the mic amplifier (IC161)
“H”: power on (rec mode)
“H”: power on (rec mode)
39
VCC
—
Power supply terminal (+3.3V)
40
AMPOW
O
Power supply on/off control signal output to the power amplifier (IC168) “H”: power on
41
SPOWER
O
Power supply on/off control signal output to the ADPCM (IC164) “H”: power on
42
MSPOW
O
Power supply on/off control signal output to the memory stick “H”: power on
43
VSS
—
Ground terminal
44 to 50
A17 to A11
O
Address signal output to the static RAM (IC727)
51
VSS
—
Ground terminal
– 40 –
Pin No.
Pin Name
I/O
Description
52
A10
O
Address signal output to the static RAM (IC727)
53
VCC
—
Power supply terminal (+3.3V)
54 to 59
A9 to A4
O
Address signal output to the static RAM (IC727)
60
VCC
—
Power supply terminal (+3.3V)
61
VSS
—
Ground terminal
62 to 64
A3 to A1
O
Address signal output to the static RAM (IC727)
65
PC0
I
Not used (open)
66
VCC
—
Power supply terminal (+3.3V)
67
VSS
—
Ground terminal
68
RXD2
I
Serial reception data input from the real time clock (IC721) and EEPROM (IC723)
69
TXD2
O
Serial transmission data output to the ADPCM (IC164), real time clock (IC721) and EEPROM
(IC723)
(IC723)
70
SCK2
O
Serial data transfer clock signal output to the ADPCM (IC164), real time clock (IC721) and
EEPROM (IC723)
EEPROM (IC723)
71
XDDEN
O
DSP control interface enable signal output to the ADPCM (IC164) “L” active
72
XDPDN
O
Power down control signal output to the ADPCM (IC164) “L”: power down
73
SP/LP
O
Filter switching signal output terminal “L”: SP mode, “H”: LP mode Not used
74
BTLSE
O
BTL/SE switching signal output terminal “L”: SE mode, “H”: BTL mode
75
VSS
—
Ground terminal
76
XLCDRST
O
Reset signal output to the liquid crystal display module (LCD720) “L”: reset
77
XBCK
O
DSP bit clock signal output to the ADPCM (IC164)
78
LCDSCK
O
Serial data transfer clock signal output to the liquid crystal display module (LCD720)
79
VCC
—
Power supply terminal (+3.3V)
80
BATTCTL
I
Not used
81
FWECTL
O
FWE control signal output terminal “L” active Connected to the FWE (pin <zz. ) in this set
82
VSS
—
Ground terminal
83
VCC
—
Power supply terminal (+3.3V)
84
LMUTE
O
Line muting control signal output terminal “H”: line muting on
85
HPMUTE
O
Muting control signal output to the earphone “H”: muting on
86
VSS
—
Ground terminal
87
EPRST
O
Reset signal output to the EEPROM (IC723) “L”: reset
88
BEEPCTL
O
Beep sound control signal output terminal “L”: beep sound on
89 to 92
D15 to D12
I/O
Two-way data bus with the static RAM (IC727)
93
VCC
—
Power supply terminal (+3.3V)
94
D11
I/O
Two-way data bus with the static RAM (IC727)
95
VSS
—
Ground terminal
96 to 102
D10 to D4
I/O
Two-way data bus with the static RAM (IC727)
103
VSS
—
Ground terminal
104
VCC
—
Power supply terminal (+3.3V)
105 to 108
D3 to D0
I/O
Two-way data bus with the static RAM (IC727)
109
VSS
—
Ground terminal
110
MODE0
I
Setting terminal for the CPU operational mode (fixed at “H” in this set)
111
MODE1
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
112
VCC
—
Power supply terminal (+3.3V)
113
EXTAL
I
Main system clock input terminal (3.7706 MHz)
114
VSS
—
Ground terminal
115
XTAL
O
Main system clock output terminal (3.7706 MHz)
– 41 –
Pin No.
Pin Name
I/O
Description
116
VCC
—
Power supply terminal (+3.3V)
117
MODE2
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
118
MODE3
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
119
FWE
I
FWE control signal input terminal “L” active
Connected to the FWECTL (pin ia) in this set
Connected to the FWECTL (pin ia) in this set
120
WAKEUP
I
Key interruption processing start signal output terminal
121
XRST
I
System reset signal input from the reset signal generator (IC726) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
122
VSS
—
Ground terminal
123
CKIO
I/O
Not used (open)
124
VCC
—
Power supply terminal (+3.3V)
125
XHSTBY
I
Not used (fixed at “H”)
126
XWDTOVF
O
Not used (open)
127
MODE4
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
128
MODE5
I
Setting terminal for the CPU operational mode (fixed at “L” in this set)
129
PLLVSS
—
Ground terminal (for PLL)
130
PLLCAP1
I
Connected to the external capacitor for PLL
131
PLLCAP2
I
Connected to the external capacitor for PLL
132
PLLVCC
—
Power supply terminal (+3.3V) (for PLL)
133
RXPROG
I
Not used
134
VSS
—
Ground terminal
135
XTAL32
O
Sub system clock output terminal Not used (open)
136
EXTAL32
I
Sub system clock input terminal Not used (fixed at “H”)
137
VCC
—
Power supply terminal (+3.3V)
138
TXPROG
O
Not used
139
KEYPUP
O
Key power control signal output terminal
140
VSS
—
Ground terminal
141
CK
—
Not used (open)
142
VCC
—
Power supply terminal (+3.3V)
143
VSS
—
Ground terminal
144
HPJACK
I
Earphone jack detection signal input terminal “L”: earphone in
145
REDLED
O
LED drive signal output terminal of the rec indicator (D761 red) “H”: LED on (rec mode)
146
GRNLED
O
LED drive signal output terminal of the play indicator (D761 green)
“H”: LED on (play mode)
“H”: LED on (play mode)
147
XVORIN
I
Detect whether audio signal is entered or not input from the VOR detection circuit (IC163)
“L”: signal is entered, “H”: signal is not entered
“L”: signal is entered, “H”: signal is not entered
148
RTCINTR
I
Not used
149
RTCINT1
I
Alarm interruption signal and regular period interruption signal input from the real time clock
(IC721)
(IC721)
150
XDCIN
I
DC power supply detection signal input terminal “L”: DC power supply, “H”: dry battery
151
MSEJ
I
Memory stick insert detection signal input terminal
“L”: memory stick in, “H”: memory stick out
“L”: memory stick in, “H”: memory stick out
152
VSS
—
Ground terminal
153
XEPBUSY
I
Ready/busy detection signal input from the EEPROM (IC723) “L”: busy
154
PULLUP
O
Power supply output terminal (+3.3V)
155
PE22
O
Not used (open)
156
PE23
O
Not used (open)
– 42 –
Pin No.
Pin Name
I/O
Description
157
PF1
O
Not used (open)
158
PF2
O
Not used (open)
159
SYNC
O
FS sync signal output to the ADPCM (IC164)
160
LIGHT
O
LED drive signal output terminal of the liquid crystal display module (LCD720) back light
indicator (D720) “H”: LED on
indicator (D720) “H”: LED on
161
VCC
—
Power supply terminal (+3.3V)
162
PF6
O
Not used (open)
163
PF7
O
Not used (open)
164
VSS
—
Ground terminal
165
AVSS
—
Ground terminal (for A/D converter)
166
XHOLD
I
HOLD switch (S761) input terminal “L”: HOLD on, “H”: HOLD off
167 to 170
KEYIN3 to
KEYIN0
I
Key return signal input from the key matrix “L” input when key pressing
171
VORSW
I
VOR switch (S764) input terminal “L”: VOR on, “H”: VOR off
172
SPEED
I
PLAY SPEED select switch (S763) input terminal (A/D input)
“L”: SLOW, “M”: FAST, “H”: NORMAL
“L”: SLOW, “M”: FAST, “H”: NORMAL
173
BATT
I
Dry battery power supply voltage detection signal input terminal (A/D input)
174
TEST1
I
Setting terminal for the test mode Not used (fixed at “H”)
175
TEST2
I
Setting terminal for the test mode “L”: test mode (normally: fixed at “H”)
176
AVCC
—
Power supply terminal (+3.3V) (for A/D converter)
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