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9

This set provides the checks given below in TEST MODE.

Turn on power to the set. Turn on [V-UP] switch from the off state
while pressing  b  key and [Camera] button at the same time.

Press [RESET] switch.

The menu given below appears when TEST MODE is entered.

Select an item using  >  /  .  key and determine the selected
item using  u  key.

Check the version of each module.

ICX-165 build: Language

(JP: Japanese, US: English, and CN: Chinese)

ARM : F/W version for CPU (ARM unit)
SHE

: F/W version for SUB-CPU

DSP

: F/W version for CPU (DSP unit)

IPL

: F/W version for IPL

Date

: Build date and time

Check the input by pressing each key.

Input and INT check (KEY input acceptance check and
KEY_XWAKE interrupt check).
Target input keys:
[MACRO] / [CAM-DET] / [HOLD] / [DISPLAY/MENU] /  u /
  >  /  . /  b  /  B  /  x  / [VOL +] / [VOL --] / [V-UP] /
[CAMERA] / [CAPTURE] / [REC/PAUSE] / [LCD COVER]
Total of 17 key locations

The backlight is lit for 0.5 sec. when a key input is accepted.

Check the languages and change between them.
The default is Japanese.
Example of LCD display

Perform a DSP LOOP BACK.

Sound 1.3kHz beep.

Perform three types of self tests: NOR, NAND and PORT.
OK is displayed if normal operation is confirmed by the test.

Check the current value of Battery A/D.

Check the current value of DC-IN A/D.
NG is displayed if not connected.

Check the presence of VBUS.
OK is displayed if VBUS is present.

Perform a sleep test.
The LCD display disappears and then the sleep mode is entered.
To exit the sleep mode, press [RESET] switch.

MicSens
Lcd Contrast
Key Check
Initialize
Version
F/W Update

LCD display

.

>

Determine using   

u  

key.

     :
MicSens
Lcd Contrast
Key Check
Initialize
Version
F/W Update
Camera Init
Camera Adjust
Language
Loop Back
AGC
Beep
RTC Interrupt
System
Battery
DC-IN
VBUS
Sleep
Log Output
Log Clear
    :
    :

ICX-165 build JP
ARM 1.0.00
SHE 1.3
DSP 0.8.37
IPL

1.0.00

Mar 28 22:09:49

LCD display

<KEY CHECK>
KEY:- -

REMAIN:17

<KEY CHECK>
KEY:- -

OK

LCD display

Display the key of 
which input is accepted.

Total of 17 keys counted.

Once all checks have been completed,
OK is displayed and the green LED is lit.

<Language>
SET JP
[VOL +]:US
[VOL –]:JP

Example of LCD display

10

Check the AGC set value.
Verify that the set value is appropriate (VALUE=07).

Perform a self- test on RTC.

This is a log output for design.
Note: Do not use this item.

This is a log clear for design.
Note: Do not use this item.

Initialize the set values.

Perform an F/W update.

16-1. F/W Upgrade method
If the firmware is required to be updated for correction of bugs found
after mass production, the F/W should be upgraded according to
the following procedure:

(1) Connect the AC adapter and supply power from an AC outlet.
(2) Connect the set with a PC via USB and copy the following

file to the root directory in the Nancy drive. (This file is
distributed for correction of bugs found.)
* MSFWUPGR.UPG (file for upgrade)

(3) Ensure the copy is complete and disconnect USB connection.
(4) Set TEST MODE and select “F/W Update”.
(5) Press  u  key to start the F/W Update.
(6) The OPE-LED is lit red to green to orange and then lit out.

Now the update is complete.

(7) Select “Version” in TEST MODE and check the version.

The upgrade will fail if the power is off or RESET is pressed during
upgrade.
(This will result in malfunctions such as power not turned on and
incorrect operation during operation of the set.)
If this problem occurs, the set need be disassembled for upgrade.
Contact the Design Department.

Adjust the LCD contrast.
Adjustment method:
Check the color bars on the upper half of the screen and make sure
that the colors are correct.
Use  >  key to make the contrast stronger. Use  .  key to
make the contrast weaker.
By adjusting the contrast, adjust so that there are no black and white
crushes on the boundaries between 3 lines on each of the left and
right sides and that the color bars can be recognized symmetrically.

Correct the sensitivity balance of the left and right built-in
microphones due to variations in sensitivity dependent on the single
microphone.

*

Provide an anechoic box.

*

Install a speaker and a set stand in the box.

*

Fix the set on the stand. (The set should face the speaker
straight.)

*

Close the lid on the box.

*

Produce a 1kHz sinusoidal wave through the speaker. (Sound
level: 80 dBSPL or so)

*

Start adjustment using  u  key

*

Wait for 30 seconds. The adjustment is OK if OK is displayed.
NG or TIMEOUT is displayed if the adjustment fails.

*

In terms of audibility, ensure there is no difference in level
between the left and right built-in microphones.
Set the adjustment mode and place the set on the stand in the
box.

Write the initial settings to the camera module itself.

Camera adjustment (white point defect correction)
Adjustment method:
Cover the camera lens so that shadow completely is pictured before
performing this adjustment.

56

Current contrast value

These 4 boundaries 
should be recognizable 
symmetrically.

OSC 1KHz

stand

anechoic box

set

switch

set

Set the adjustment mode 
and place the set on the 
stand in the box.

11

11

ICD-CX50

Note on Schematic Diagrams:
• All capacitors are in 

µ

F unless otherwise noted.  (p: pF) 50 WV or

less are not indicated except for electrolytics and tantalums.

• All resistors are in 

Ω

 and 

1

/

4

 

W or less unless otherwise specified.

•        

f

: internal tolerance.

•

C

: panel designation.

•

A

: B+ Line.

• Power voltage is dc 3.7V and fed with regulated dc power supply

from battery terminal.

• Voltages and waveforms are dc with respect to ground under no-

signal (detuned) conditions.
no mark : PB
[           ]

  

: REC

      ∗

  

: Impossible to measure

• Voltages are taken with a VOM (Input impedance 10 M

Ω

).

Voltage variations may be noted due to normal production toler-
ances.

• Waveforms are taken with a oscilloscope.

Voltage variations may be noted due to normal production toler-
ances.

• Circled numbers refer to waveforms.

• Signal path.

F

: PB

L

: REC

*

Replacement of IC1001, 3951, 9301 and 9501 used in this set re-
quires a special tool.

• The voltage and waveform of CSP (chip size package) cannot be

measured, because its lead layout is different from that of conven-
tional IC.

Note on Printed Wiring Boards:
•

Y

: parts extracted from the conductor side.

•

: Pattern from the side which enables seeing.

(The other layers' patterns are not indicated.)

*

Replacement of IC1001, 3951, 9301 and 9501 used in this set
requires a special tool.

• Lead layouts

Lead layout of

conventional IC

CSP (chip size package)

Caution:
Pattern face side:

Parts on the pattern face side seen from

(Side B)

the pattern face are indicated.

Parts face side:

Parts on the parts face side seen from

(Side A)

the parts face are indicated.

surface

LCD board

JACK board

MAIN board

SWITCH board

MICROPHONE board

DETECTION SWITCH board 

•

MEMO

12

12

ICD-CX50

ADDT

BCLK

LRCK

DADT

CS

2

PGI0_SI 189

PGI0_CLK 187

PGI0_SEN 188

PGIO_SO 190

SIOM_CS0 175

SIOM_CS2 177

VDHY

VCCY

SHF

LED_C

4

SIOS_DATAI 184

SIOS_DATAO 185

VUNREG

IC5201

REAL TIME CLOCK

S5424

(MACRO)/z

S5423

(HOLD/CAMOP)

CAM_YUV0-7

CAM_VS

CAM_HS

IIC_SCL

IIC_SDA

CAM_IRST

CAM_PCLK

CAM_CLK_I

VDD_

CAML

VDD_

CAMH

266

271

275

270

278

269

281

267

172

VSY

RST

LP

FRX

LCD UNIT

GCP

XINH

DY

YSCL

XSCL

DA0-5

TFD_CNTV

TFD_CNTL

Q6301

MUTE

Q6401

IC6401

PWER AMP

IC1001 (1/3)

DSP

IC6601

CLOCK OSC

284

CAM_HS 283

IIC_SCL 293

IIC_SDA 294

VUNREG

282

CAM_PWR

1

IC10701

+3V REG.

1

VLCD

VDD_IO1

IC11001

+5V REG.

3

IC10801

+2.9V REG.

IC10301

+1.5V REG.

IC6301

INPUT SELECT ADC, DAC

CCD

IMAGER

IC1002

BUFFER

X6601

11.2896MHz

Q6541,6542

+B SWITCH

VDD_IO1

Q8601

DRIVER

Q11111-11112

+B SWITCH

D8601

X1001

11.2896MHz

3

5

IC8031

CLOCK GENERATOR

X8032

19.28MHz

S5422

(CAMERA DETECT)

S22207

(LCD OPEN)

SPEAKER

INCLUDED

LCD UNIT

(

)

MIC

(L-CH)

MIC22401

MIC

(R-CH)

MIC20201

m

PLUG IN

POWER

J6301

(

)

VCORE

22 20 24 30

12

13

14

19

15

25

27

26

4

6-11

6

TFD_D0-5

J3002

i

9

8

22

3

10

11

12

21-14

• Signal path

: REC

: PB