Sony ICD-B5 Service Manual ▷ View online
3
ICD-B5
SECTION 1
GENERAL
This section is extracted
from instruction manual.
from instruction manual.
Index to Parts and Controls
Main unit
MIC jack
(PLUG IN POWER)
EAR (earphone) jack
(PLUG IN POWER)
EAR (earphone) jack
OPR (operation) indicator
z
REC (record) /STOP
X
PAUSE
— .REVIEW/
>
>
+CUE
Nx
PLAY/STOP•
EXECUTE
HOLD
VOL (volume)
MIC
(built-in microphone)
Display window
FOLDER
INDEX
DISPLAY
MIC SENSE
(microphone sensitivity)
MENU
ERASE
Speaker
STOP
Rear
Battery
compartment
compartment
Hook for handstrap
(not supplied)
(not supplied)
Display window
Selected message
number/Mode
indication of the
menu (ON, OFF, etc.)
number/Mode
indication of the
menu (ON, OFF, etc.)
REC (recording)
indicator
indicator
Remaining battery
indicator
indicator
Remaining memory
indicator
indicator
Counter /Remaining time indication /Recording date
indication /Current time indication (15:30, etc.) /Menu
indication (ALARM, BEEP, etc.) /Messages (ERASE, HOLD,
etc.)
indication /Current time indication (15:30, etc.) /Menu
indication (ALARM, BEEP, etc.) /Messages (ERASE, HOLD,
etc.)
Folder indication
Alarm indicator
Repeat play indicator
Microphone sensitivity
indication
REC DATE (recorded date)
indication
REMAIN indicator
4
ICD-B5
Note : This set can be disassemble according to the following sequence.
SECTION 2
DISASSEMBLY
Note : Follow the disassembly procedure in the numerical order given.
2-1. UPPER LID ASSY
2-1.
UPPER LID ASSY
(Page 4)
(Page 4)
2-2.
F-SW BOARD,
P-SW BOARD
(Page 5)
P-SW BOARD
(Page 5)
SET
2-3.
MAIN BOARD
(Page 5)
(Page 5)
1
B 1.7x10
4
claw
2
B 1.7x7
7
screws 1.7x2.5
8
speaker (SP101)
3
claws
5
claws
9
upper lid assy
case assy
6
claw
5
ICD-B5
2-2. F-SW BOARD, P-SW BOARD
2-3. MAIN BOARD
1
CN701
2
case assy
4
F-SW board
5
P-SW board
3
Removal the five solders.
3
screw
4
claw
5
claw
case assy
1
Removal the two solders.
6
MAIN board
2
speaker (SP101)
6
ICD-B5
3-1. IC PIN DESCRIPTION
• IC703 µPD780308GC-A58-8EU (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1 to 3
KEY1 to 3
I
Key input
4
XHOLD
I
Hold switch input
5
AMPPOW
O
Power down control output for power amplifier IC (IC103).
6
AVREFON
O
A/D reference voltage input
7
XFMCE
O
Chip enable output for flash memory IC (IC701).
8
VDD0
—
Power supply pin
9
AVREF
—
A/D reference voltage
10
XFMWE
O
Write enable signal output for flash memory IC (IC701).
11
XFMALE
O
ALE signal output
12
VSS1
—
Ground
13
XFMR/B
I
Ready/Busy signal input from flash memory IC (IC701).
14
XFMCLE
O
CLE signal output for flash memory IC (IC701).
15, 16
NC
O
Not used. (Open)
17
XFMRE
O
Read enable signal output for flash memory IC (IC701).
18
XFMSE
O
SE signal output for flash memory IC (IC701).
19
XFMWP
O
WP signal output for flash memory IC (IC701).
20
CLKOUT
O
Not used. (Open)
21
BEEP
O
Beep signal output (2.4 kHz)
22
LIGHT
O
LCD back light control output
23 to 26
COM0 to 3
O
LCD common signal output
27
BIAS
O
Connect to VDD. (LCD bias)
28 to 30
VLC0 to 2
—
LCD drive power supply pin
31
VSS0
—
Ground
32 to 61
S0 to 29
O
LCD segment signal output
62
MGHIGH
I
Mic gain mode input (High: high mode)
63
MGTEST
O
Mic gain mode test output
64
XTEST
I
Test pin
65
DSPPOW
O
Digital signal processor registor control I/F enable signal output
66
LEDREC
O
OPR (REC) LED (D701: red) ON/OFF output
67
LEDPB
O
OPR (PLAY) LED (D701: green) ON/OFF output
68
RTCCE
O
Real time clock chip enable signal output
69
XDSPIFRQ
O
I/F request signal output for DSP IC (IC101).
70
DSPIFRW
O
I/F data read/write signal output for DSP IC (IC101).
71
XDSPRST
O
Reset signal output for A/D, D/A converter, DSP IC (IC101).
72
SI0
I
I/F data signal input for DSP IC (IC101).
73
SO0
O
I/F data signal output for DSP IC (IC101).
74
SCK0
O
I/F signal clock output for DSP IC (IC101).
75
RTCDI
I
Real time clock data input
76
RTCDO
O
Real time clock data and digital signal processor registor control data output
77
RTCCLK
O
Real time clock I/F data and digital signal processor registor control clock output
78
IC
—
Ground
79
X2
O
System clock output (5 MHz)
80
X1
—
System clock input (5 MHz)
81
VDD1
—
Power supply pin
82
XT1
—
Sub clock input (32.768 kHz)
83
XT2
—
Not used. (Open)
84
XRESET
I
Reset signal input
85
NC
—
Not used. (Open)
SECTION 3
DIAGRAMS
Ver 1.1