Sony ICD-B120 (serv.man2) Service Manual ▷ View online
13
13
ICD-B120
ICD-B120
(Page 12)
4-4. SCHEMATIC DIAGRAM — MAIN BOARD (2/2) — • Refer to page 14 for Waveforms.
• Refer to page 15 for IC Pin Description.
R709
R710
S701
TP704
TP703
TP702
C711
C712
C731
C732
S706
S707
S708
S709
S702
S703
S704
S705
R749
R750
R751
R752
R745
R746
R747
R748
IC703
R733
R721
R720
C702
R706
R707
R714
W7001
W7002
W7003
W7004
W7005
W7006
R523
C701
X702
C708
C707
C743
C716
C715
R703
R702
CN701
D702
TP701
R701
Q702
D701
LCD701
Q703
R736
R734
X701
IC702
R727
R726
R728
R711
R712
R713
R753
IC701
14
14
ICD-B120
ICD-B120
• IC BLOCK DIAGRAMS
IC506 XC9105D091MR
IC102 MM3111AWLE
• Waveforms
— MAIN Board —
1
IC703
qj
(OSC1)
0.5 V/DIV, 0.1
µ
sec/DIV
2
IC703
w;
(XI)
0.5 V/DIV, 20
µ
sec/DIV
32.768 kHz
1.1 Vp-p
8 MHz
1.3 Vp-p
5
BUFFER
DRIVER
DRIVER
PHASE
COMPENSATION
PHASE
COMPARATOR
RAMP WAVE
GENERATOR,
OSC
4
CURRENT
RIPPLE DETED
AND FB
VREF WITH
SOFT START,
CE
PWM/PFM
CONTROLER
ERROR
AMP
1
2
3
FB
VDD
CE
EXT
GND
1
BIAS
3
4
2
8
6
5
7
SHUTDOWN
BYPASS
+IN
-IN
VO2
GND
VDD
VO1
15
ICD-B120
• IC PIN DESCRIPTION
IC703 MN101C74FSB (MEMORY CONTROL, SYSTEM CONTROL) (MAIN BOARD (2/2))
Pin No.
Pin Name
I/O
Pin Description
1 to 4
COM0 to 3
O
LCD common signal output 0 to 3
5 to 7
VLC3 to 1
I
LCD reference power supply input
8
C2
I
Connect to VLC1 (pin 7).
9
XFLMPWR
O
Not used in this set. (Open)
10
XREDLED
O
Red LED on/off signal output
11
XGRNLED
O
Green LED on/off signal output
12
XHPMUTE
O
Headphone mute signal output “L”: Mute
13
AMPPWR
O
Power amplifier power control signal output “H”: ON, “L”: OFF
14
NC
O
Not used. (Open)
15
DSPDPWR
O
DSP power control signal output “H”: ON, “L”: OFF
16
VSS
—
Ground pin
17
OSC1
I
High speed frequency signal input (8 MHz)
18
OSC2
O
High speed frequency signal output (8 MHz)
19
VDD
—
Power supply pin (+3 V)
20
XI
I
Low speed frequency signal input (32.768 kHz)
21
XO
O
Low speed frequency signal output (32.768 kHz)
22
NMOD
I
Connect to ground.
23
XRESET
I
Reset signal input
24
DMOD
I
Connect to VDD.
25
VREF
I
A/D converter power supply pin (+3 V)
26
BATT
I
Battery level signal input
27, 28
KEYIN0, 1
I
Key signal input
29, 30
NC
O
Not used. (Open)
31
SCK3
O
Not used in this set. (Open)
32
SO3 (VBUS)
O
Not used in this set. (Open)
33
SI3 (D+)
O
Not used in this set. (Open)
34
RTCCS (D–)
O
Not used in this set. (Open)
35
BATTEN (VSS)
O
Battery level sense enable signal output “L”: Enable
36
SHIMUKE (FM SCK)
I
Destination information
37
TX (FM SDAO)
O
Not used in this set. (Open)
38
RX (FM SDAI)
I
Not used in this set. (Open)
39
SCKI (DSP)
O
DSP serial clock signal output
40
SO1 (DSP)
O
DSP serial data signal output
41
SI1 (DSP)
I
DSP serial data signal input
42
XDSPRST
O
DSP reset signal output “L”: Reset
43
DSPIFREQ
O
DSP interface request signal output
44
DSPIFRW
O
DSP interface read/write signal output
45
LMUTE
O
Audio mute signal output
46
DSPCLKOUT
O
DSP system clock signal output
47
BEEP
O
Beep signal output
48
WAKEUP
I
Wake up signal input
49
HOLDSW
I
Hold switch signal input
50
P22OUT (FM SCE)
O
Not used in this set. (Open)
51
XDCINDET
I
Power supply input detect signal input “L”: IN
52
XDSPIFACK
I
DSP acknowledge signal input
53
RESERVED (FM PWR)
O
Not used in this set. (Open)
54
FLMRB
I
Flash memory ready/busy signal input
55
XFLMWP
O
Flash memory write protect signal output
56
XFLMCSO
O
Flash memory chip select signal output
57
FLMCLE
O
Flash memory common lutch enable signal output
58
FLMALE
O
Flash memory address lutch enable signal output
16
ICD-B120
Pin No.
Pin Name
I/O
Pin Description
59
XFLMWE
O
Flash memory write enable clock signal output
60
XFLMRE
O
Flash memory read enable clock signal output
61 to 68
FLMIO0 to 7
I/O
Flash memory address/data signal input/output 0 to 7
69 to 100
SEG31 to 0
O
LCD segment signal output 31 to 0
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