Sony ICD-B10 / ICD-B15 Service Manual ▷ View online
8
ICD-B10/B15
2-2. F-SW BOARD
Note : This set can be disassemble according to the following sequence.
SECTION 2
DISASSEMBLY
Note : Follow the disassembly procedure in the numerical order given.
2-1. SUB BLOCK ASSY, UPPER LID
Set
Sub Block Assy, Upper Lid
F-SW Board
Main Board
1
screw (B1.7x10)
6
sub block assy, upper lid
case assy
4
claw
3
claws
5
2
screw (B1.7x7)
7
screws (B1.7x2.5)
8
speaker
1
CN703
case assy
3
F-SW board
2
9
ICD-B10/B15
2-3. MAIN BOARD
3
screw (B1.7x10)
2
speaker
1
Removal the solders
6
MAIN board
4
claw
5
claw
case assy
10
ICD-B10/B15
3-1. IC PIN DESCRIPTIONS
• IC712 MB90523APFF-G-116-BND (SYSTEM CONTROL)
Pin No.
Pin Name
I/O
Pin Description
1
RTCCE
O
Real-time clock chip enable signal output
2
BEEP
O
Beep signal output
3
XFLMRE
O
Flash memory read enable signal output
4
XFLMWE
O
Flash memory write enable signal output
5
FLMRB
I
Flash memory R/B signal input
6
DSPPWR
O
DSP power supply signal output
7
ADASYSCK
O
ADA codec system clock signal output
8
VCC
—
Power supply pin
9
DSPSYSCK
O
DSP system clock signal output
10
XZRST
O
Zephy reset signal output
11
DSPACK
O
DSP I/F acknowledge signal output
12
XDIFEN
O
DSP I/F enable signal output
13
DCOMDT
O
DSP I/F command/data signal output
14
SIN1
I
DSP I/F serial data signal input
15
SOT1
O
DSP I/F serial data signal output
16
SCK1
O
DSP I/F serial clock signal output
17 – 32
SEG00 – 15
O
LCD segment signal output
33
VSS
—
Ground pin
34
C
—
C (Connect to power supply pin.)
35
SIN2
I
Zephyr/RTC I/F serial data signal input
36
SOT2
O
Zephyr/RTC I/F serial data signal output
37
SCK2
O
Zephyr/RTC I/F serial clock signal output
38
DVCC
—
Digital power supply pin
39
DVSS
—
Digital ground pin
40
ZIFACK
O
Zephyr I/F acknowledge signal output
41
SIPCS
O
Serial parallel converter IC I/F chip enable signal output
42
AVCC
—
Analog power supply pin
43
AVRH
—
A/D reference voltage H (Connect to VCC.)
44
AVRL
—
A/D reference voltage L (Connect to ground.)
45
AVSS
—
Analog ground pin
46
BATT
I
Battery level detection A/D signal input
47
KEYIN0
I
Key A/D signal input 0
48
KEYIN1
I
Key A/D signal input 1
49
SPEED
I
Speed switch A/D signal input
50
XVORSW
I
VOR switch signal input (Low: VOR switch ON)
51
HPJACK
I
Headphone jack ON/OFF signal input (Not used in this set.)
52
FLMSEL
I
Flash memory select A/D signal input
53
KEYPUP
O
Key pull-up signal output
54
VCC
—
Power supply pin
55
FLMALE
O
Flash memory address latch enable signal output (AND: OE)
56
FLMCLE
O
Flash memory command enable signal output (AND: CDE)
57
XVORIN
I
VOR signal input
58
XDSPRST
O
DSP reset signal output
59 – 62
COM0 – 3
O
LCD common signal output
63
VSS
—
Ground pin
64 – 72
SEG16 – 24
O
LCD segment signal output
73
SUBXTAL
O
Sub clock oscillation pin (Not used in this set.)
74
SUBCLK
I
Sub clock oscillation signal input (32.768 kHz)
SECTION 3
DIAGRAMS
ICD-B10/B15
11
11
Pin No.
Pin Name
I/O
Pin Description
75 – 81
SEG25 – 31
O
LCD segment signal output
82 – 85
V0 – 3
—
LCD driver reference power supply pin
86
XHSTBY
I
Hardware standby signal input
87
MD2
I
Operation mode signal input 2
88
MD1
I
Operation mode signal input 1 (Connect to VCC.)
89
MD0
I
Operation mode signal input 0
90
XRESET
I
Reset signal input
91
VSS
—
Ground pin
92
XTALIN
I
Main oscillation signal input (4.096 MHz)
93
XTAL
O
Main oscillation signal output (4.096 MHz)
94
VCC
—
Power supply pin
95
WAKEUP
I
Wake up signal input
96
DSPIFREQ
I
DSP voice I/F request signal input
97
ZIFREQ
I
USB microcomputer (zephyr) I/F request signal input
98
RTCINTR
I
Real-time clock interruption request signal input
99
VBUSOFF
I
USB Vbus ON/OFF detection signal input (H=OFF)
100
HOLDSW
I
Hold switch signal input (High: HOLD)
101
XFLMCEO
O
Flash memory chip enable 0 signal output
102
XFLMRST/CE1
O
Flash memory reset signal/chip enable 1 signal output
103 – 110
FLMIO00 – 07
I/O
Flash memory data bus
111 – 118
FLMIO08 – 15
I/O
Flash memory data bus (Not used in this set.)
119
VSS
—
Ground pin
120
XFLMWP
O
Flash memory write protect signal output
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