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Model
ICD-47
Pages
18
Size
1.45 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
icd-47.pdf
Date
PREV: Sony SRS-P7 Service Manual

Sony ICD-47 Service Manual ▷ View online

ICD-47
10
10
• IC Block Diagrams
IC101
MC145481SDR2
+ 
–
8
13
1
2
20
0.886 V
REF
H. P. F.
SEQUENCE
AND
CONTROL
SHARED
DAC
DAC
ADC
RECEIVE SHIFT
REGISTER
TRANSMIT SHIFT
REGISTER
VAG REF
RO–
4
PO–
3
PI
6
VDD
5
PO+
DR
9
BCLKR
10
PDI
7
FSR
DT
12 BCLKT
11 MCLK
14 FST
15 VSS
16 MU/A
VAG
19 TI+
18 TI–
17 TG
1
VDD
VSS
CUT OFF
FREQUENCY: 200 Hz
L. P. F.
CUT OFF
FREQUENCY: 3.4 kHz
L. P. F.
CUT OFF
FREQUENCY: 3.4 kHz
– 
+
–1
IC102
NJM2076M (TE2)
INVA IN
NON INVB IN
BASE B
BASE A
A OUT
VSS
B OUT
2
VDD
3
1
4
7
6
5
8
POWER
AMP
POWER
AMP
IC106
XC25BS5001MR
3
4
1
2
6
Q1
VDD
CLKIN
CE
Q0
5
VSS
1
2
1
4
11 BIT PLL
(
×
N)
IC107
AN6123MS-TXL
GM
5
DET
3
IN
4
GND
2
DET
1
VCC
DET
IC501
XC6372C331PR
IC502
XC6372D351PR
NC
VOUT
CE
VSS
LX
2
1
3
4
5
VLX
LIMITER
PWM/PFM
CONTROL
OSC 100kHz
BUFFER
PHASE
COMPARATOR
REFERENCE
VOLTAGE
CHIP
ENABLE
SLOW
START
+
–
VDD
IC503,  506
XC62GR3312MR
+ 
–
3
OUTPUT
CONTROL
REFERENCE
VOLTAGE
4
1
2
5
CURRENT
LIMIT
VSS
VIN
CE
NC
VOUT
IC703
RS5C348A-E2
VDD
VDD
OSCIN
OSCOUT
CE
/INTR
32KOUT
SCLK
SO
SI
VSS
32 kHz
OUTPUT
CONTROL
COMPARATOR
W
COMPARATOR
D
ADDRESS
REGISTER
I/O
CONTROL
ADDRESS
DECODER
SHIFT
REGISTER
INTERRUPT
CONTROL
OSC
DETECT
VOLTAGE
DETECT
ALARM W REGISTER
(WEEK, MIN, HOUR)
ALARM D REGISTER
(MIN, HOUR)
DIV
OSC
DIVIDER
CORRECTION
9
10
8
7
6
2
3
4
5
1
TIMER COUNTER
SEC, MIN, HOUR, WEEK,
DAY, MONTH, YEAR
11
ICD-47
• Waveforms
1
IC101 
7
 (FSR), 
qf
 (FST)
IC104 
rd
 (SLDA)
1 V/DIV, 50 
µ
s/DIV
3.4 Vp-p
150 
µ
s
2
IC101 
9
 (BCLKR), 
qa
 (MCLK),
qs
 (BCLKT), IC104 
rs
 (SCLK)
1 V/DIV, 200 ns/DIV
3
IC104 
es
 (XTALA), IC106 
6
 (Q0)
1 V/DIV, 100 ns/DIV
4
IC106 
3
 (CLKIN), IC701 
qg
 (DSPMCK)
1 V/DIV, 20 
µ
s/DIV
5
IC701 
ul
 (X2)
2 V/DIV, 100 ns/DIV
6
IC701 
is
 (XT1), IC703 
1
 (32KOUT)
1 V/DIV, 10 
µ
s/DIV
7
IC701 
ij
 (RTCINT), IC703 
6
 (INTR)
2 V/DIV, 200 ms/DIV
8
IC703 
8
 (OSCOUT)
200 mV/DIV, 10 
µ
s/DIV
9
IC501 
4
 (LX)
1 V/DIV, 5 
µ
s/DIV
0
IC502 
4
 (LX)
2 V/DIV, 5 
µ
s/DIV
qa
Q502 (Base)
200 mV/DIV, 5 
µ
s/DIV
qs
Q502 (Collector)
1 V/DIV, 5 
µ
s/DIV
3.4 Vp-p
565 ns
4.6 Vp-p
282 ns
73.5 
µ
s
3.4 Vp-p
3.6 Vp-p
200 ns
2.5Vp-p
30.6 
µ
s
4.3 Vp-p
500 ms
1.1 Vp-p
30.6 
µ
s
4.3 Vp-p
9.9 
µ
s
3.6 Vp-p
11.2 
µ
s
0.9 Vp-p
11.1 
µ
s
4.6 Vp-p
3.6 
µ
s
12
ICD-47
5-4.
IC  PIN  FUNCTION  DESCRIPTION
•
 IC104  1609J--VA11H-DB (DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VDD
—
Power supply terminal (+3.3V)
2
RDY
O
Interrupt output terminal of ready/busy detection signal to the system controller (IC701)
“L”: ready, “H”: busy
3
SLDB
I/O
Not used (open)
4
OSCBYP
I
Not used (fixed at “H”)
5
INTB
I
Not used (open)
6 to 11
IOPA7 to IOPA2
I/O
Not used (open)
12
VSS
—
Ground terminal
13
VDD
—
Power supply terminal (+3.3V)
14, 15
IOPA1, IOPA0
I/O
Not used (open)
16
MDISDO
O
Recording serial data output to the system controller (IC701)    “H” active
17
MDISDI
I
Playback serial data input from the system controller (IC701)    “H” active
18
SCK
I
Serial clock signal input from the system controller (IC701)    “H” active
19
SSN
I
Transmission status input from the system controller (IC701)    “L” active
20
TDO
O
Not used (open)
21
TDI
I
Not used (open)
22
VSS
—
Ground terminal
23
VDD
—
Power supply terminal (+3.3V)
24
TCK
I
Not used (open)
25
TMS
I
Not used (open)
26
IOPD3
I/O
Not used (open)
27
RWN
O
Not used (open)
28
IOPD1
I
Stop signal input from the system controller (IC701)    “L” active
29
IOPD0
O
Interrupt output terminal of frame signal to the system controller (IC701)    “H” active
30
VSS
—
Ground terminal
31
XTALB
I/O
Not used (fixed at “L”)
32
XTALA
I
PLL clock signal (4.096 MHz) input from the divider (IC106)    “H” active 
33
VSSA
—
Ground terminal
34
VDDA
—
Power supply terminal (+3.3V)
35
VPP
—
Not used (open)
36
DAV
O
Available data output to the system controller (IC701)   “H” active 
37
RSTB
I
Reset signal and power down detection signal input from the system controller (IC701)
“L”: reset or power down
38
VDD
—
Power supply terminal (+3.3V)
39
VSS
—
Ground terminal
40
SDI
I
Recording serial data input from the ADPCM (IC101)
41
SDO
O
Playback serial data output to the ADPCM (IC101)
42
SCLK
O
Serial clock signal output to the ADPCM (IC101)
43
SLDA
O
Serial data output to the ADPCM (IC101)
44
VSS
—
Ground terminal
13
ICD-47
•
 IC701  
µ
PD780308GC-A31-8EU (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
KEY0
I
Key input terminal (A/D input)    S701 to S705 (STOP, REC START/STOP, Nx PLAY/STOP
(EXECUTE), – . (SELECT), > + (SELECT) ) keys input
2
KEY1
I
Key input terminal (A/D input)    S707 to S709 (MENU, FILE, ERASE) keys input
3
SPDSW
I
PLAY SPEED select switch (S712) input terminal (A/D input)
“L”: SLOW, “M”: FAST, “H”: NORMAL
4
XHOLD
I
HOLD switch (S711) input terminal    “L”: HOLD ON, “H”: HOLD OFF
5
LMUTE
O
Line muting control signal output terminal    “H”: line muting on
6
MICSEL
O
Microphone sensitivity select signal output terminal
“L”: mic sensitivity low, “H”: mic sensitivity high
7
XFMCE
O
Chip enable signal output to the flash memory (IC702)    “L” active
8
VDD0
—
Power supply terminal (+3.3V)
9
AVREF
I
Reference voltage input terminal (for A/D converter)
10
XFMWE
O
Write enable signal output to the flash memory (IC702)    “L” active
11
XFMALE
O
Address latch enable signal output to the flash memory (IC702)    “L” active
12
VSS1
—
Ground terminal
13
XFMBSY
I
Ready/busy detection signal input from the flash memory (IC702)    “L” active
14
XFMCLE
O
Command latch enable signal output to the flash memory (IC702)    “L” active
15
DSPMCK
O
Sampling frequency sync signal output to the digital signal processor (IC104)    “H” active
16
DSPSSN
O
Transmission status output to the digital signal processor (IC104)    “L” active
17
XFMRE
O
Read enable signal output to the flash memory (IC702)    “L” active
18
NC
—
Not used (open)
19
XFMWP
O
Write protect signal output to the flash memory (IC702)    “L” active
20
XFMSE
O
Spare space enable signal output to the flash memory (IC702)    “L” active
21
BEEP
O
Beep sound drive signal output terminal (2.4 kHz)    “H” active
22
PLLCRL
O
Serial data transfer clock signal output to the divider (IC106)
Power on/off control signal output for the ADPCM (IC101), digital signal processor (IC104),
divider (IC106) and LED power supply    “H”: power on
23 to 26
COM0 to COM3
O
Common drive signal output to the liquid crystal display (ND701)    “H” active
27
BIAS
O
Power supply output terminal for the liquid crystal display (ND701)    “H” active
28 to 30
VLC0 to VLC2
I
Power supply input terminal for the liquid crystal display (ND701)    “H” active
31
VSS0
—
Ground terminal
32 to 61
S0 to S29
O
Segment drive signal output to the liquid crystal display (ND701)    “H” active
62
NC
—
Not used (open)
63
APOWER
O
Power on/off control signal output for the mic amplifier (IC103) and AGC (IC107)
“H”: power on (rec mode)
64
XTEST
I
Setting terminal for the test mode    “L”: test mode (Normally: fixed at “H”)
65
DSPSTP
O
Stop signal output to the digital signal processor (IC104)    “L” active
66
LEDREC
O
LED drive signal output of the REC indicator (D504 red)    “H”: LED on (rec mode)
67
LEDPB
O
LED drive signal output of the PLAY indicator (D504 green)    “H”: LED on (play mode)
68
AMPPOW
O
Power on/off control signal output to the power amplifier (IC102)
“H”: power on (play mode)
69
XSPOWER
O
Power on/off control signal output for analog power supply to the DC/DC converter circuit
“L”: power on
70
RTCCE
O
Chip enable signal output to the real time clock (IC703)    “H” active
71
DSPRST
O
Reset signal and power down detection signal output to the digital signal processor (IC104)
“H”: reset or power down
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