Sony HTC-W555 / MHC-W555 Service Manual ▷ View online
– 50 –
IC102 BA5941FP
IC103 CXD2519Q
+
–
LEVEL SHIFT
+ –
+
–
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
LEVEL SHIFT
+ –
+
–
MUTE
+
–
+
–
LEVEL SHIFT
+ –
+
–
LEVEL SHIFT
+ –
+
–
+
–
15
16
17
18
19
21
20
22
26
25
24
23
+
–
NC
Vcc
Vcc
Vcc
VCC
BIAS IN
IN1B
IN1A
IN2B
IN2A
GND
GND
MUTE
VCC
OUT2A
OUT2B
OUT1A
OUT1B
IN4B
IN4A
IN3B
IN3A
OP OUT
OP IN (–)
OP IN (+)
GND
NC
VCC
OUT3A
OUT3B
OUT4A
OUT4B
3RD-ORDER NOISE SHAPER
+
–
+
–
PWM
PWM
+
–
+
–
VDD
VSS
LMUT
RMUT
TES2
CKOUT
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
SPOC
SPOD
XLON
FOK
VDD
VSS
MON
MDP
MDS
LOCK
PWMI
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15 16 17 18 19 20
21 22 23 24 25 26 27 28 29 30
LRCK
WDCK
ASYE
ASYO
ASYI
BIAS
RF
AVDD
CLTV
AVSS
FILI
FILO
PCO
VCTL
V16M
VCKI
VPCO1
VPCO2
TES1
TES0
43
42
41
40
39
38
37
36
35
34
33
32
31
50
49
48
47
46
45
44
NC
AVSS
AVDD
AOUT1
AIN1
LOUT1
AVSS
XVDD
XTAI
XTAO
XVSS
AVSS
LOUT2
AIN2
AOUT2
AVDD
AVSS
NC
NC
XRST
88
89
90
91
92
93
94
95
96
97
98
99
100
81
82
83
84
85
86
87
SYSM
VDD
VSS
EXCK
SBSO
SCOR
WFCK
EMPHI
EMPH
DOUT
C4M
FSTT
XTSL
MNT0
MNT1
MNT3
XROF
C2PO
RFCK
GFS
XPCK
XUGF
GTOP
VDD
VSS
BCKI
BCK
PCMDI
PCMD
LRCKI
71
70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
80 79 78 77 76 75 74 73 72
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CLOCK
GENERATOR
D / A
INTERFACE
DIGITAL CLV
SERIAL-IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
SUB CODE
PROCESSOR
TIMING
LOGIC
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
ERROR
CORRECTOR
16K RAM
DIGITAL OUT
OSC
EFM
DEMODURATOR
– 51 –
• Deck section
IC602 uPC1330HA
IC701 M54641L
• CD motor section
IC801 BA6286N
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1 CONT
GND
VCC
SW P2 GND
SW R2
1
5
2
7
3
6
4
POWER
AMP.
AMP.
POWER
AMP.
AMP.
CONTROL
INPUT
AMP.
INPUT
AMP.
REG
8
VCC
VCC
REFERENCE
OUT2
OUT1
IN1
IN2
GND
1
2
3
2
3
4
5
6
5
6
7
8
9
8
9
10
TSD
CONTROL
LOGIC
PO WER
SAVE
GND
RIN
VREF
OUT2
OUT2
RNF
GND
VM
VCC
FIN
OUT1
– 52 –
6-17. IC PIN FUNCTIONS
• IC101 FOCUS/TRACKING/SLED SERVO RF AMP (CXA1992AR)
Pin No.
Pin Name
I/O
Function
FEO
FEI
FDFCT
FGD
FLB
FE O
FE M
SRCH
TGU
TG2
FSET
TA M
TA O
SL P
SL M
SL O
ISET
V
CC
LOCK
CLK
XLT
DATA
XRST
C.OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
RF I
RF O
O
I
I
I
I
O
I
I
I
I
I
I
O
I
I
O
I
I
I
I
I
I
I
O
O
O
O
I
O
I
I
I
O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Focus error amplifier output
Connected internally to the window comparator input for bias adjustment
Focus error input
Capacitor connection pin for defect time constant
Ground this pin through a capacitor for cutting the focus servo high-frequency gain
External time constant setting pin for boosting the focus servo low-frequency
Focus drive output
Focus amplifier inverted input
External time constant setting pin for generating focus search waveform
External time constant setting pin for switching tracking high-frequency gain
External time constant setting pin for switching tracking high-frequency gain
Peak frequency setting pin for focus and tracking phase compensation amplifier
Tracking amplifier inverted input
Tracking drive output
Sled amplifier non-inverted input
Sled amplifier inverted input
Sled drive output
Connect an external capacitance to set the current which determines the Focus search,
Track jump, and Sled kick heights
Positive power supply
The sled overrun prevention circuit operates when this pin is Low (No pull-up resistance)
Serial data transfer clock input from CPU (No pull-up resistance)
Lach input from CPU (No pull-up resistance)
Serial data input from CPU (No pull-up resistance)
Reset input; resets at Low (No pull-up resistance)
Track number count signal output
Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the com-
mand from CPU
Outputs DFCT2, MIRR, BALL, TGL, FOL,and others according to the command from
CPU
Focus OK comparator output
Input for the defect bottom hold output with capacitance coupled
Defect bottom hold output
Connected internally to the interruption comparator input
Connection pin for defect bottom hold capacitor
Connection pin for MIRR hold capacitor
MIRR comparator non-inverted input
Input for the RF summing amplifier output with capacitance coupled
RF summing amplifier output
Eye-pattern check point
• Abbreviation
FZC
FZC
: Focus zero-cross
DFCT : Defect
TZC
TZC
: Tracking zero-cross
BALH : E-F Balance (High)
TGH
TGH
: Tracking Gain (High)
FOH
: Focus Bias (High)
ATSC : Anti Shock
MIRR : Mirror
BALL : E-F Balance (Low)
TGL
MIRR : Mirror
BALL : E-F Balance (Low)
TGL
: Tracking Gain (Low)
FOL
: Focus Bias (Low)
– 53 –
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Pin No.
Pin Name
I/O
Function
RF M
RFTC
LD
PD
PD1
PD2
FE BIAS
F
E
EI
V
EE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
FZC
I
I
O
I
I
I
I
I
I
–
–
O
I
I
I
I
I
O
I
RF summing amplifier inverted input
The RF amplifier gain is determined by the resistance connected between this pin and
RFO pin
External time constant setting pin during RF level control
APC amplifier output
APC amplifier input
RF I-V amplifier inverted input
Connect these pins to the photo diode A+C and B+D pins
Bias adjustment of focus error amplifier
Leave this pin open for automatic adjustment
F I-V and E I-V amplifier inverted input
Connect these pins to photo diodes F and E
I-V amplifier E gain adjustment
(When not using automatic balance adjustment)
Negative power supply
Tracking error amplifier output
E-F signal is output
Comparator input for balance adjustment
(Input from TEO through LPF)
Tracking error input
Window comparator input for ATSC detection
Trackig zero-cross comparator input
Capacitor connection pin for defect time constant
(V
CC
+ V
EE
)/2 direct voltage output
Focus zero-cross comparator input
• Abbreviation
APC : Auto Power Control
APC : Auto Power Control
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