Sony HT-SS500 / STR-KS500 Service Manual ▷ View online
25
STR-KS500
IC1602
PCM1803DBR
DELTA-SIGMA
MODULATOR
DELTA-SIGMA
MODULATOR
VINL 1
VINR 2
VREF1 3
VREF2 4
VCC
AGND
5
6
BYPAS 8
TEST 9
LRCK 10
REFERENCE
×
1/64,
×
1/128
DECIMATION
FILTER
WITH
HIGH-PASS
FILTER
SERIAL
INTERFACE
&
MODE/FORMAT
CONTROL
MODE1
20
MODE0
19
FMT1
18
FMT0
17
OSR
16
SCKI
15
VDD
14
DGND
13
DOUT
12
BCK
11
CLOCK & TIMING CONTROL
POWER
SUPPLY
PDWN 7
– MAIN Board –
IC401
M61542FP
2
1
55
53
56
54
16
17
3
4
5
6
5 INPUT SELCTOR
7
8
9
10
11
12
15
13
19
18
20 21 22 23 24
25 26 27 28
5 INPUT SELCTOR
45
29
30
32
31
VOLUME
14
INPUT ATT
(FOR ADC)
(FOR ADC)
INPUT ATT
(FOR ADC)
(FOR ADC)
36
35
33
34
VOLUME
37
38
40
39
VOLUME
GND
SRC
SLOUT
SLC
SLC
SLVIN
SLIGO
CIGO
CVIN
CVC
COUT
COUT
SWOUT
SWC
SWVIN
SWIGO
SLOUT
RECR2
RECR1
RECL1
LIGO
LVIN
LV
C
LOUT
ROUT
RVC
RVIN
RIGO
SRIGO
SRVIN
RECL2
INL5
INR5
INL4
INR4
INL3
INR3
INL2
INR2
INL1
INR1
ADIFL
ADIFR
GND
LIN
RIN
SLIN
SRIN
CIN
SWIN
GND
GND
D
ATA
CLOCK
DVDD
A
VCC
GND
AVEE
44 43
41
42
VOLUME
52 51
49
50
VOLUME
46
48 47
VOLUME
MCU I/F
26
STR-KS500
– DISPLAY Board –
IC152
µ
PD16315GB-3BS
5
OSC
OSC
DATA
SELECTOR
6
DOUT
7
DIN
8
CLK
9
STB
10
KEY1
11
KEY2
SERIAL
INTERFACE
DISPLAY MEMORY
24 BITS x 12 WORDS
24-BIT OUTPUT
LATCH
12-BIT SHIFT
REGISTER
SEGMENT
DRIVER
TIMING GENERATOR
KEY SCAN
COMMAND
DECODER
DIMMING
CIRCUIT
KEY DATA MEMORY
(2 x 16 BITS)
4-BIT LATCH
1
LED1
2
LED2
3
LED3
4
LED4
24
16
16
12
4
8
8
4
8
27 SEG14/KS14
29 SEG16/KS16
30 VEE
28 SEG15/KS15
8
31 SEG17/GRID12
33 SEG19/GRID10
32 SEG18/GRID11
23 SEG10/KS10
24 SEG11/KS11
25 SEG12/KS12
26 SEG13/KS13
22
SEG9/KS9
21
SEG8/KS8
20
SEG7/KS7
19
SEG6/KS6
18
SEG5/KS5
17
SEG4/KS4
16
SEG3/KS3
15
SEG2/KS2
14
SEG1/KS1
MULTIPLEXED
DRIVER
34
SEG20/GRID9
35
SEG21/GRID8
36
SEG22/GRID7
37
SEG23/GRID6
39
GRID4
40
GRID3
41
GRID2
42
GRID1
43
VDD
44
VSS
13
VDD
12
VSS
38
SEG24/GRID5
GRID
DRIVER
27
STR-KS500
•
IC Pin Function Description
DIGITAL BOARD IC1501 CXD9862R (AUDIO DIGITAL SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
VSS
-
Ground terminal
2
XRST
I
System reset signal input from the system controller "L": reset
3
EXTIN
I
Master clock signal input terminal Not used
4
LRCKI3
I
L/R sampling clock signal input terminal Not used
5
VDDI
-
Power supply terminal (+1.85V)
6
BCKI3
I
Bit clock signal input terminal Not used
7
PLOCK
O
Internal PLL lock signal output terminal Not used
8
VSS
-
Ground terminal
9
MCLK1
I
System clock input terminal (13.9 MHz)
10
VDDI
-
Power supply terminal (+1.85V)
11
VSS
-
Ground terminal
12
MCLK2
O
System clock output terminal (13.9 MHz)
13
MS
I
Master/slave setting terminal "L": internal clock, "H": external clock
Fixed at "L" in this set
Fixed at "L" in this set
14
SCKOUT
O
Internal system clock output to the D/A converter
15
LRCKI1
I
L/R sampling clock signal input from the digital audio interface receiver
16
VDDE
-
Power supply terminal (+3.3V)
17
BCKI1
I
Bit clock signal input from the digital audio interface receiver
18
SDI1
I
Audio serial data input from the A/D converter
19
LRCKO
O
L/R sampling clock signal output to the D/A converter
20
BCKO
O
Bit clock signal output to the D/A converter
21
VSS
-
Ground terminal
22
KFSIO
I
Audio clock signal input from the digital audio interface receiver
23 to 25
SDO1 to SDO3
O
Audio serial data output to the D/A converter
26
SDO4
O
Audio serial data output terminal Not used
27
SPDIF
O
SPDIF signal output terminal Not used
28
LRCKI2
I
L/R sampling clock signal input from the digital audio interface receiver
29
BCKI2
I
Bit clock signal input from the digital audio interface receiver
30
SDI2
I
Audio serial data input from the digital audio interface receiver
31
VSS
-
Ground terminal
32
HACN
O
Acknowledge signal output to the system controller
33
HDIN
I
Serial data input from the system controller
34
HCLK
I
Serial data transfer clock signal input from the system controller
35
HDOUT
O
Serial data output to the system controller
36
HCS
I
Chip select input from the system controller
37
GP12
I
Write signal input from the system controller
38
GP13
O
SD-RAM chip enable output terminal Not used
39
GP14
O
Row address strobe signal output terminal Not used
40
VDDI
-
Power supply terminal (+1.85V)
41
VSS
-
Ground terminal
42
GP15
O
Column address strobe signal output terminal Not used
43
OE0
O
Output enable signal output to the S-RAM
44
CS0
O
Chip select signal output to the S-RAM
45
WE0
O
Write enable signal output to the S-RAM
46
VDDE
-
Power supply terminal (+3.3V)
47
WMD1
I
External memory wait mode setting terminal Fixed at "H" in this set
28
STR-KS500
Pin No.
Pin Name
I/O
Description
48
VSS
-
Ground terminal
49
WMD0
I
External memory wait mode setting terminal Fixed at "H" in this set
50
PAGE2
O
External memory page selection signal output terminal Not used
51
VSS
-
Ground terminal
52, 53
PAGE1, PAGE0
O
External memory page selection signal output terminal Not used
54
BOOT
I
Boot mode control signal input terminal Not used
55
TST1
O
Not used
56
BST
I
Boot strap signal input from the system controller
57
MOD1
I
Operation mode setting terminal "L": enhanced mode, "H": normal mode
Fixed at "H" in this set
Fixed at "H" in this set
58
MOD0
I
Operation mode setting terminal "L": single chip mode, "H": can not use
Fixed at "L" in this set
Fixed at "L" in this set
59
EXLOCK
I
PLL lock error signal and data error flag input from the digital audio interface receiver
60
VDDI
-
Power supply terminal (+1.85V)
61
VSS
-
Ground terminal
62, 63
A17, A16
O
Address signal output terminal Not used
64 to 66
A15 to A13
O
Address signal output to the S-RAM
67
GP10
I
L/R sampling clock signal input terminal Not used
68
GP9
O
Read ready signal output to the system controller
69
GP8
I
Channel status bit 1 input from the digital audio interface receiver
70
VDDI
-
Power supply terminal (+1.85V)
71
VSS
-
Ground terminal
72 to 75
D15 to D12
I/O
Two-way data bus with the S-RAM
76
VDDE
-
Power supply terminal (+3.3V)
77 to 80
D11 to D8
I/O
Two-way data bus with the S-RAM
81
VSS
-
Ground terminal
82 to 85
A9, A12 to A10
O
Address signal output to the S-RAM
86
TDO
O
Simplicity emulation data output terminal Not used
87
TMS
I
Simplicity emulation data input start and end terminal Not used
88
XTRST
I
Simplicity emulation non-sync break signal input terminal Not used
89
TCK
I
Simplicity emulation clock signal input terminal Not used
90
TDI
I
Simplicity emulation data input terminal Not used
91
VSS
-
Ground terminal
92 to 97
A8 to A3
O
Address signal output to the S-RAM
98, 99
D7, D6
I/O
Two-way data bus with the S-RAM
100
VDDI
-
Power supply terminal (+1.85V)
101
VSS
-
Ground terminal
102 to 105
D5 to D2
I/O
Two-way data bus with the S-RAM
106
VDDE
-
Power supply terminal (+3.3V)
107, 108
D1, D0
I/O
Two-way data bus with the S-RAM
109, 110
A2, A1
O
Address signal output to the S-RAM
111
VSS
-
Ground terminal
112
A0
O
Address signal output to the S-RAM
113
PM
I
PLL initialize signal input from the system controller "L": initialize
114, 115
SDI3, SDI4
I
Audio serial data input terminal Not used
116
SYNC
I
Sync/non-sync setting terminal "L": sync, "H": non-sync Fixed at "H" in this set
117
TST2
I
Not used
118
GP11
I
Not used
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