Sony HT-SL5A / TA-KSL5 Service Manual ▷ View online
25
TA-KSL5
3-16. IC PIN FUNCTION DESCRIPTIONS
• IC1201 CXD9617R (AUDIO DSP) (DIGITAL BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23-25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
—
I
I
I
—
I
O
—
I
—
—
I/O
I
O
I/O
—
I/O
I
O
O
—
I/O
O
O
O
I
I
I
—
O
I
I
O
I
O
O
O
—
—
O
O
O
O
—
I
—
I
O
—
O
Pin Name
VSS
XRST
EXTIN
FS2
VDD1
FS1
PLOCK
VSS
MCLK1
VDD1
VSS
MCLK2
MS
SCKOUT
LRCKI1
VDDE
BCKI1
SDI1
LRCKO
BCKO
VSS
KFSIO
SDO1-SDO3
SDO4
SPDIF
LRCKI2
BCKI2
SDI2
VSS
HACN
HDIN
HCLK
HDOUT
HCS
SDCLK
CLKEN
RAS
VDDI
VSS
CAS
DQM/OE0
CSO
WEO
VDDE
WMD1
VSS
WMD0
PAGE2
VSS
PAGE1
Description
Ground terminal
Rest input from the system control
Not used (Ground)
Not used (Ground)
+2.5V
Not used (Ground)
Internal PLL lock signal output (TP1201)
Ground terminal
Clock pulse input
+2.5V
Ground terminal
Clock pulse input-output
Not used (Ground)
Internal system and clock power output to the CODEC (IC1501)
Not used
+3.3V
Bit clock input-output terminal for audio interface serial data (TP1202)
Data input from the CODEC (IC1501)
Sampling clock output to the CODEC (IC1501)
Bit clock output to the CODEC (IC1501)
Ground terminal
Audio clock (384fs/256fs) input from the DIR (IC1101)
Serial data output to the CODEC (IC1501)
Serial data output terminal (TP1203)
SPDIF power output terminal (TP1204)
Sampling clock input to the DIR (IC1101)
Bit clock input from the DIR (IC1101)
Data input from the DIR (IC1101)
Ground terminal
Acknowledge output to the system control (IC1601)
Serial data input from the system control (IC1601)
Clock input from the system control (IC1601)
Serial data output to the system control (IC1601)
Chip selection input from the system control (IC1601)
SDRAM clock (TP1205)
SDRAM clock enable (TP1206)
Row address strobing (TP1207)
+2.5V
Ground terminal
Column address strobing (TP1208)
Data I/O mask (TP1209)
Chip selection output to the SRAM (IC1202)
Write enable output to the SRAM (IC1202)
+3.3V
Setting for external memory WAIT mode (pull up)
Ground terminal
Setting for external memory WAIT mode (pull up)
ERAM page switch (TP1210)
Ground terminal
ERAM page switch (TP1211)
26
TA-KSL5
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64-66
67-69
70
71
72-75
76
77-80
81
82-85
86
87
88
89
90
91
92-97
98,99
100
101
102-105
106
107,108
109,110
111
112
113
114
115
116
117-119
120
Pin Name
PAGE0
BOOT
BTACT
BST
MOD1
MOD0
EXLOCK
VDDI
VSS
A17
A16
A15-A13
GP10-GP8
VDDI
VSS
D15-D12
VDDE
D11-D8
VSS
A9-A10
TDO
TMS
XTRST
TCK
TDI
VSS
A8-A3
D7,D6
VDDI
VSS
D5-D2
VDDE
D1,D0
A2,A1
VSS
A0
PM
SD13
SD14
SYNC
VSS
VDDI
I/O
O
I
O
I
I
I
I
—
—
O
O
O
I/O
—
—
I/O
—
I/O
—
O
O
I
I
I
I
—
O
I/O
—
—
I/O
—
I/O
O
—
O
I
I
I
I
—
—
Description
ERAM page switch (TP1212)
Not used (Ground)
Boot mode status display signal (TP1213)
Boot strap signal input from the system control (IC1601)
Setting for 256fs (pllx9) (pull up)
Setting for single chip mode (pull down)
Lock signal input terminal
+2.5V
Ground terminal
External memory address (TP1214)
External memory address (TP1215)
Address signal output to the SRAM (IC1202)
External memory data I/O general purpose port terminal GP
+2.5V
Ground terminal
SRAM (IC1202) data signal I/O terminal
+3.3V
SRAM (IC1202) data signal I/O terminal
Ground terminal
Address signal output to the SRAM (IC1202)
Simple emulation data output (TP1216)
Simple emulation data entry beginning and the end terminal (TP1217)
Asynchronous simple BREAK input terminal of emulation (TP1218)
Simple emulation clock input (TP1219)
Simple emulation data entry (TP1220)
Ground terminal
Address signal output to the SRAM (IC1202)
SRAM (IC1202) data signal I/O terminal
+2.5V
Ground terminal
SRAM (IC1202) data signal I/O terminal
+3.3V
SRAM (IC1202) data signal I/O terminal
Address signal output to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
PLL initialization input from the system control (IC1601)
Data entry terminal (TP1221)
Data entry terminal (TP1222)
Synchronization / asynchronous selection terminal (L:Sync. H:Async.)
Ground terminal
+2.5V
27
TA-KSL5
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I
I
O
O
I
O
O
O
O
O
—
O
O
O
O
O
O
I
O
O
O
O
—
O
I
O
I
I
O
I
I
I
O
I/O
—
—
—
I
I
I
I
—
I
I
I
I
I
I
I
I
Pin Name
DATA O
GP9
BEST
HCS
HACN
XRST
PM
PD
SMUTE
CDT1
VSS
SCL
CS
DATA
CLK
LATCH
WOOFER RELAY
HDOUT
HDIN
HCLK
F MUTE
VIDEO SW1
VCC5
ANA/DIG
HD DETECT
VIDEO SW2
FLASH2
FLASH1
VIDEO MUTE
MODE
2CH
AFD
SCL
SDA
AVCC
AVRH
AVSS
A/D0
A/D1
A/D2
A/D3
VSS
NOT IN USE
MODEL
VERSION
NC
CRYSTAL SEL
STOP
MD0
MD1
Description
Data input from the DIR (IC1101)
External memory data input from the DSP (IC1201)
Boot strap signal output to the DSP (IC1201)
Chip selection signal output to the DSP (IC1201)
Acknowledge signal input from the DSP (IC1201)
Reset signal output to the DSP (IC1201)
PLL initialization signal output to the DSP (IC1201)
PD signal output to the CODEC (IC1501)
Smute signal output to the CODEC (IC1501)
CDT1 signal output to the CODEC (IC1501)
Ground terminal
Serial clock signal output to the CODEC (IC1501)
Chip selection signal output to the CODEC (IC1501)
Serial control data output to the IC401
Serial control clock output to the IC401
Latch signal to the IC401
Sub woofer relay control signal output
Serial data input from the DSP (IC1201)
Serial data output to the DSP (IC1201)
Clock signal output to the DSP (IC1201)
Function mute signal output
Video switch signal output to the IC201
+3.3V (STBY)
Function mute and error port signal output
Not used
Video switch signal output to the IC201
Flash programming input
Flash programming input
Video mute signal output to the IC201
Not used
Not used
Not used
SCL signal output to the EEPROM (IC1604)
SDA signal from the EEPROM (IC1604)
+3.3V(STBY)
+3.3V(STBY)
Ground terminal
Not used
Not used
Key data signal input from S101-104
Key data signal input from S111-115
Ground terminal
Ground terminal
Model detection input (Ground terminal)
Version resisrtor input (Ground terminal)
Not used
Not used
Power stop detection signal input
Flash programming MD0 input
Not used (connected to +3.3V(STBY))
• IC1601 MB90478PF-G-129-BND (SYSTEM CONTROL) (DIGITAL BOARD)
28
TA-KSL5
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87-92
93
94
95
96
97
98
99
100
Pin Name
MD2
NOT IN USE
NOT IN USE
SIRCS
FUSE DETECT
POWER KEY
JOG(B)
JOG(A)
VOL(B)
VOL(A)
DIN
CLK
FL_STB
FAN_ON
FAN_CLK
POWER RELAY
PROTECTOR
F_CTRL2
F_CTRL1
REAR RELAY
CENTER RELAY
FRONT RELAY
TUNED
STEREO
MUTE
DO
RSTX
SLATCH
X1A
X0A
VSS
XO
XI
VCC3
NOT IN USE
NC
NOT IN USE
XMODE
CKSEL1
CLK
CE
DI
DO
ERROR
XSTATE
I/O
I
I
I
I
I
I
I
I
I
I
O
O
O
I
I
O
I
O
O
O
O
O
I
I
O
I
I
O
—
—
—
O
I
—
I
I
I
O
O
O
O
O
I
I
I
Description
Flash programming MD2 input
Ground terminal
Ground terminal
Data input from the remote control receiver
Connected to +3.3V through the resistor (47k ohm)
Power swich detection signal input
Not used
Not used
Volume signal input from the rotary encoder
Volume signal input from the rotary encoder
Serial control data output to the FL/LED driver (IC152)
Clock signal output to the FL/LED driver (IC152)
STB signal output to the FL/LED driver (IC152)
Fan on detection signal input
Feedback signal input from the fan (FAN901)
Power relay drive signal output
Protect detection signal input
Fan speed control signal output
Fan ON/OFF control signal output
Surround relay drive signal output
Center relay drive signal output
Front relay drive signal output
Tuning a frequency detection signal input from the tuner (not used)
STEREO tuning signal from the tuner (not used)
Muting control signal output from the tuner (not used)
Data input from the tuner (not used)
System reset input
Serial control latch signal output to the tuner (not used)
Not used
Not used (connected to ground terminal)
Ground terminal
Terminal for a oscillator
Terminal for a oscillator
+3.3V (STBY)
Not used
Not used
Not used
Reset signal output to DIR (IC1101)
Not used
Clock signal output to DIR (IC1101)
Chip enable signal output to DIR (IC1101)
Write data output to DIR (IC1101)
Read data input from DIR (IC1101)
“PLL lock error, data error flag input from DIR (IC1101)”
Source clock selection monitor input from DIR (IC1101)
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