Sony HT-SL50 / HT-SL55 / HT-SL70 / STR-KSL50 Service Manual ▷ View online
17
17
STR-KSL50
3-9. Schematic Diagram – Display Section –
• See page 18 for IC Block Diagrams.
S111
S112
S113
C142
C158
C159
R178
S114
S115
S116
R192
R153
C141
C143
C155
C156
R191
R194
S123
IC102
C112
R198
D154
D153
D152
R152
CN151
CNP152
CN153
C157
D151
R176
RV101
R199
FL101
IC152
0.1
0.1
0.1
82k
1k
100
10
50V
1000p
220p
220p
1k
1k
NJL74H400A
47
16V
1
SELS5B23C
SELS5B23C
SELS523C
10
17P
3P
3P
10 50V
SELS5B23C
150
1
18
18
STR-KSL50
IC1101 LC89056W (DIGITAL Board)
38
37
36
23
24
1
2 3
4
5
44
8 9 10
46
17
22
21
20
30
35
25
26
27
28
29
32
33
34
16
45
13
14
15
47
40
41
48
CL
39
XSEL
CE
DI
EMPHA
AUDIO
DISEL
DOUT
DINO
DINI
DIN2
6
DGND
7
DVDD
11
AVDD
12
AGND
DOSEL0
R
VIN
LPF
CKSEL0
XSTATE
18 DGND
19 DVDD
XIN
XOUT
XMCK
DVDD
31
DGND
DO
CSFLAG
F0/P0/C0
F1/P1/C1
F2/P2/C2
F3/P3/C3
AUTO
BPSYNC
ERROR
DATAO
DOSEL1
CKOUT
BCK
LRCK
CKSEL1
MODE0
MODE1
42
DGND
43
DVDD
XMODE
TIMING
MICROCOMPUTER
INTERFACE
SAMPLING
FREQUENCY
C BIT
DETECT
PA/PB
DETECT
LOCK
DETECT
SYSTEM
RESET
MODE
SELECT
INPUT
CIRCUIT
DATA
DEMODULATOR
PLL
CLOCK
VIN3
V-
14
SW2
13
VIN1
12
MUTE1
11
VOUT1
10
NC
9
V+
8
1
SW1
2
AMP
VIN2
3
MUTE2
4
VOUT2
5
GND2
6
GND1
7
AMP
11
KEY2
10
KEY1
9
STB
8
CLK
7
DIN
6
DOUT
5
DSC
4
VIDEO LED
3
DVD LED
2
TV/SAT LED
1
33
TUNER LED
GRID10
32
GRID11
31
GRID12
30
VEE
29
SEG16
28
SEG15
27
SEG14
26
SEG13
25
SEG12
24
SEG11
23
SEG10
44
12
VSS
VSS
13
VDD
14
SEG1
15
SEG2
16
SEG3
17
SEG4
18
SEG5
19
SEG6
20
SEG7
21
SEG8
22
SEG9
43
VDD
42
GRID1
41
GRID2
40
GRID3
39
GRID4
38
GRID5
37
GRID6
36
GRID7
35
GRID8
34
GRID9
SERIAL
INTERFACE
24-bit
OUTPUT LATCH
DATA SELECTOR
12-bit
SHIFT REGISTER
4-bit
LATCH
DISPLAY MEMORY
24 bits x 12 words
KEY DATA MEMORY
(2 x 16 bits)
TIMING GENERATOR
KEY SCAN
COMMAND DECODER
GRID DIRVER
MULTIPLEXED
DRIVER
DIMMING
CIRCUIT
OSC
OSC
R
SEGMENT DRIVER
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
FORMAT
CONVERTER
AUDIO
INTERFACE
INPUT
CIRCUIT
OUTPUT
CIRCUIT
CIRCUIT
LOOP1
LOOP0/SDA/CDTI
DIF1/SCL/CCLK
DIF0/CSN
P/SN
MCLK
DZF1
AVSS
AVDD
VREFH
VCOM
DZF2
RIN+
RIN–
LIN+
LIN–
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
DEM1
DEM0
TVDD
DVDD
DVSS
PDN
ICKS2
ICKS1
ICKS0
CAD1
CAD0
SDOS
I2C
SMUTE
BICK
LRCK
SDTI1
SDTI2
SDTI3
SDTO
DAUX
DFS
IC1501 AK4527B (DIGITAL Board)
INR10/RECR4
AVEE
INL9
INR9
INL8
INR8
INL7
INR7
SLIN2
INL6
INIR6
INL5
INR5
INL4
INR4
INL3
NC
RSELOUT
GND
NC
SWVIN
LATCH
CLOCK
DGND
SLVIN
SWIN2
CIN2
SWSELOUT
SROUT
LIN1
SRIN2
NC
GND
GND
AVCC
NC
RIN1
SWIN1
DVDD
RIN2
LIN2
GND
BALANCE R/-
BALANCE R/+
SRSELOUT
SRIN1
ROUT
LOUT
CIN1
GND
INR1
INL1
INR2
RECR2
INR3
BALANCE L/+
SWOUT
COUT
NC
BALANCE L/-
RVIN
CVIN
CSELOUT
SLSELOUT
GND
SLOUT
NC
SRVIN
SLIN1
LVIN
LSELOUT
GND
RECL1
RECR1
RECL2
RECL3
RECR3
INL10/RECL4
DATA
INL2
MCU I/F
CLK
DATA
LATCH
80
78
77
76
75
74
73
72
71
70
69
68
67
66
65
79
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
1
2
3
4
5
6
7
8
9
10
11
12
13 14
15
16 17
18
19
20
21
22
23
24
IC201 NJM2279D (MAIN Board)
IC152
µ
PD16315GB-3BS (DISPLAY Board)
IC401 M61527FP (MAIN Board)
3-10. IC Block Diagram
19
STR-KSL50
3-11. IC Pin Function Descriptions
• IC1201 CXD9617R (AUDIO DSP) (DIGITAL BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23 to 25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
I/O
—
I
I
I
—
I
O
—
—
—
—
—
I
O
I/O
—
I/O
I
O
O
—
I/O
O
O
O
I
I
I
—
O
I
I
O
I
O
O
O
—
—
O
O
O
O
—
I
—
I
O
—
O
Pin Name
VSS
XRST
EXTIN
FS2
VDD1
FS1
PLOCK
VSS
MCLK1
VDDI
VSS
MCLK2
MS
SCKOUT
LRCKI1
VDDE
BCKI1
SDI1
LRCKO
BCKO
VSS
KFSIO
SDO1 to SDO3
SDO4
SPDIF
LRCKI2
BCKI2
SDI2
VSS
HACN
HDIN
HCLK
HDOUT
HCS
SDCLK
CLKEN
RAS
VDDI
VSS
CAS
DQM/OE0
CS0
WE0
VDDE
WMD1
VSS
WMD0
PAGE2
VSS
PAGE1
Description
Ground terminal
Rest input from the system control
Not used (connected to the ground)
Not used (connected to the ground)
Power supply terminal (+2.5V)
Not used (connected to the ground)
Internal PLL lock signal output Not used (open)
Ground terminal
Resonator terminal (13.5MHz)
Power supply terminal (+2.5V)
Ground terminal
Resonator terminal (13.5MHz)
Master/slave operation selection terminal (L : internal clock) (fixed at “L”)
Internal system clock output to the CODEC (IC1501)
Not used (open)
Power supply terminal (+3.3V)
Bit clock input-output terminal for audio interface serial data Not used (open)
Data input from the CODEC (IC1501)
Sampling clock output to the CODEC (IC1501)
Bit clock output to the CODEC (IC1501)
Ground terminal
Audio clock (384fs/256fs) input from the DIR (IC1101)
Serial data output to the CODEC (IC1501)
Serial data output terminal Not used (open)
SPDIF power output terminal Not used (open)
Sampling clock input to the DIR (IC1101)
Bit clock input from the DIR (IC1101)
Data input from the DIR (IC1101)
Ground terminal
Acknowledge signal output to the system control (IC1601)
Serial data input from the system control (IC1601)
Clock input from the system control (IC1601)
Serial data output to the system control (IC1601)
Chip select signal input from the system control (IC1601)
SDRAM clock Not used (open)
SDRAM clock enable Not used (open)
Row address strobing Not used (open)
Power supply terminal (+2.5V)
Ground terminal
Column address strobing Not used (open)
Data I/O mask Not used (open)
Chip select signal output to the SRAM (IC1202)
Write enable signal output to the SRAM (IC1202)
Power supply terminal (+3.3V)
Setting WAIT mode for external memory (pull up)
Ground terminal
Setting WAIT mode for external memory (pull up)
External memory page switch signal output Not used (open)
Ground terminal
External memory page switch signal output Not used (open)
20
STR-KSL50
Pin No.
53
54
55
56
57
58
59
60
61
62
63
64 to 66
67
68
69
70
71
72 to 75
76
77 to 80
81
82 to 85
86
87
88
89
90
91
92 to 97
98,99
100
101
102 to 105
106
107,108
109,110
111
112
113
114
115
116
117 to 119
120
Pin Name
PAGE0
BOOT
BTACT
BST
MOD1
MOD0
EXLOCK
VDDI
VSS
A17
A16
A15 to A13
GP10
GP9
GP8
VDDI
VSS
D15/GP7 to D12/GP4
VDDE
D11/GP3 to D8/GP0
VSS
A9 to A10
TDO
TMS
XTRST
TCK
TDI
VSS
A8 to A3
D7,D6
VDDI
VSS
D5 to D2
VDDE
D1,D0
A2,A1
VSS
A0
PM
SD13
SD14
SYNC
VSS
VDDI
I/O
O
I
O
I
I
I
I
—
—
O
O
O
O
O
I
—
—
I/O
—
I/O
—
O
O
I
I
I
I
—
O
I/O
—
—
I/O
—
I/O
O
—
O
I
I
I
I
—
—
Description
External memory page switch signal output Not used (open)
Not used (connected to the ground)
Boot mode status display signal Not used (open)
Boot strap signal input from the system control (IC1601)
Setting for 256fs (pllx9) (pull up)
Setting for single chip mode (pull down)
Lock signal input terminal
Power supply terminal (+2.5V)
Ground terminal
External memory address Not used (open)
External memory address Not used (open)
Address signal output to the SRAM (IC1202)
LRCK0 signal output
GP9 (DECODE) signal output to the system control (IC1601)
GP8 (AUDIO) signal input from the DIR (IC1101)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
Simple emulation data output Not used (open)
Simple emulation data entry beginning and the end terminal Not used (open)
Asynchronous simple BREAK input terminal of emulation Not used (open)
Simple emulation clock input Not used (open)
Simple emulation data entry Not used (open)
Ground terminal
Address signal output to the SRAM (IC1202)
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+2.5V)
Ground terminal
Data input/output from/to the SRAM (IC1202)
Power supply terminal (+3.3V)
Data input/output from/to the SRAM (IC1202)
Address signal output to the SRAM (IC1202)
Ground terminal
Address signal output to the SRAM (IC1202)
PLL initialization signal input from the system control (IC1601)
Data entry terminal Not used (open)
Data entry terminal Not used (open)
Synchronization / asynchronous selection terminal (L:Sync. H:Async.) (fixed at “H”)
Ground terminal
Power supply terminal (+2.5V)
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