DOWNLOAD Sony HT-CT550W / STR-CT550WT Service Manual ↓ Size: 3.1 MB | Pages: 64 in PDF or view online for FREE

Model
HT-CT550W STR-CT550WT
Pages
64
Size
3.1 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
ht-ct550w-str-ct550wt.pdf
Date
PREV: Sony HT-CT550W / SA-WCT550W Service Manual

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STR-CT550WT
45
MAIN  BOARD  IC1002  R5F364AMDFA (SYSTEM  CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
DAMP_SCDT/DIR_DI
O
Serial data output to the stream processor and digital audio interface receiver
2
DAMP_SHIFT/
DIR_CLK
O
Serial data transfer clock signal output to the stream processor and digital audio interface 
receiver
3
SIRCS_IN
I
SIRCS signal input from the remote control receiver
4
N.A
O
Not used
5
DSP MOSI
O
Serial data output to the DSP
6
DSP MISO
I
Serial data input from the DSP
7
DSP_SPICLK
O
Serial data transfer clock signal output to the DSP
8
BYTE
I
External data bus width selection signal input terminal    Fixed at “L” in this unit
9
CNVss
I
Processor mode selection signal input terminal
10
ROM_SDA
I/O
Two-way data bus with the EEPROM
11
ROM_SCLK
O
Serial data transfer clock signal output to the EEPROM
12
RESET
I
System reset signal input from the reset signal generator    “L”: reset    
For several hundreds msec. after the power supply rises, “L” is input, then it change to “H”
13
Xout
O
System clock output terminal (6 MHz)
14
Vss
-
Ground terminal
15
Xin
I
System clock input terminal (6 MHz)
16
Vcc1
-
Power supply terminal (+3.3V)
17
CEC(I/O)
I/O
CEC serial data input/output with the HDMI connector
18
DIR_ZERO
I
Zero data detection signal input from the digital audio interface receiver
19
DIR_CSFLAG
O
Not used
20
DRIVE_OCP(DIAG)
I
Shut down signal input from the power amplifi er    “L”: shut down 
21
FAN_CTRL
O
Fan motor control signal output terminal    Not used 
22 to 26
N.A
O
Not used
27
DIR ERROR
I
Error detection signal input from the digital audio interface receiver    “L”: error
28
N.A
O
Not used
29
S-AIR_I2C_SDL
I/O
Two-way I2C clock bus with wireless transceiver
30
S-AIR_I2C_SDA
I/O
Two-way I2C data bus with wireless transceiver
31
M_TX_OUT
O
Serial data output to the DSP
32
M_RX_IN
I
Serial data input from the DSP
33
SCD/CLK1
I
Not used
34
BUSY/RTS1
I
Not used
35
MC_STDO/ST_SDA
I/O
Two-way data bus with the FM receiver
36
ST_CLK/ST_SCL
O
Serial data transfer clock signal output to the FM receiver
37
N.A
O
Not used
38
HDMI_CNVSS
O
Writing mode selection signal output to the HDMI controller    “H”: writing mode
39
A_SEL1
O
Audio selection signal output terminal    Not used
40
A_SEL0
O
Audio selection signal output terminal
41
HOLD/RDS_DATA
I
RDS serial data input terminal    Not used
42
ST_CE
O
Chip enable signal output terminal    Not used
43
MC_STDO
O
Serial data output terminal    Not used
44
ST_CLK
O
Serial data transfer clock signal output terminal    Not used
45
MC_STDI
I
Serial data input terminal    Fixed at “H” in this unit
46
WR/TUNED/ST
I
Tuned detection signal input terminal    Fixed at “H” in this unit
47
HDMI TX
O
Serial data output to the HDMI controller
48
HDMI RX
I
Serial data input from the HDMI controller
49
HDMI_MUTE
I
HDMI muting on/off control signal input terminal
50
DSP_SPIDS
O
Chip select signal output to the DSP and serial fl ash
51
DSP_RESET
O
Reset signal output to the DSP   “L”: reset
52
SF_HOLD
O
Hold signal output to the serial fl ash
53
DIR_HCE
O
Chip enable signal output to the digital audio interface receiver
54
DIR_XSTATE
I
Source clock selection monitor input from the digital audio interface receiver
55
DIR_RST
O
Reset signal output to the digital audio interface receiver    “L”: reset
56
N.A
O
Not used
57
LED1
O
LED drive signal output terminal    Not used
58
N.A
O
Not used
59
SEL_HDMI
O
HDMI input selection signal output to the multiplexer
60
P_CONT4
O
Power supply on/off control signal output terminal for the DSP    “H”: power on
STR-CT550WT
46
Pin No.
Pin Name
I/O
Description
61
P_CONT3
O
Power supply on/off control signal output terminal for the fl uorescent indicator tube    
“H”: power on
62
Vcc2
-
Power supply terminal (+3.3V)
63
N.A
O
Not used
64
Vss
-
Ground terminal
65, 66
P_CONT2, P_CONT1
O
Power supply on/off control signal output terminal    “H”: power on
67
S-AIR GPIO2
O
Interrupt signal output to the wireless transceiver
68
DSP_INTR
I
Interrupt request signal input from the DSP
69
DAMP_SOFT_MUTE
O
Soft muting on/off control signal output to stream processor    “L”: muting on
70
DAMP_INIT
O
Reset signal output to the stream processor    “L”: reset
71
DAMP_LATCH1
O
Serial data latch pulse signal output to the stream processor
72
DAMP_LATCH3
O
Serial data latch pulse signal output terminal    Not used
73
AC_CUT
I
AC cut detection signal input terminal    “L”: AC cut is detected
74
KEY_INT
I
Key wake-up signal input terminal
75
RDS INT/CLK
I
RDS interrupt signal input from the FM receiver
76
DC_DET
I
Speaker DC detection signal input terminal    “L”: speaker DC is detected
77
FL_DATA
O
Serial data output to the fl uorescent indicator tube
78
FL_CS
O
Chip select signal output to the fl uorescent indicator tube
79
FL_CLK
O
Serial data transfer clock signal output to the fl uorescent indicator tube
80
OVERFLOW2
I
Overfl ow detection signal input from the stream processor
81
DRIVE_RST(EN)
O
Reset signal output to the power amplifi er    “L”: reset
82
DAMP_NSP_MUTE
O
NSP muting on/off control signal output terminal    Not used
83
HDMI_RESET
O
Reset signal output to the HDMI controller    “L”: reset
84
P_CONT_HDMI
O
Power on/off control signal output terminal for the HDMI section    “H”: power on
85
OVERFLOW1
I
Overfl ow detection signal input from the stream processor
86
P_LINK_SW
O
Not used
87
P_CONT_MAIN
O
Power supply on/off control signal output terminal    “H”: power on
88
S-AIR Reservd1
O
Not used
89
S-AIR_RST
O
Reset signal output to the wireless transceiver    “L”: reset
90
S-AIR_DET
I
Wireless transceiver connection detection signal input terminal    
“L”: wireless transceiver is connected
91
S-AIR_RF
I
RF signal input from the wireless transceiver
92
DESTINATION
I
Destination setting terminal
93
MODEL
I
Model setting terminal
94, 95
KEY2, KEY1
I
Front panel key input terminal (A/D input)
96
AVss
-
Ground terminal
97
KEY0
I
Front panel key input terminal (A/D input)
98
Vref
I
Reference voltage (+3.3V) input terminal
99
AVcc
-
Power supply terminal (+3.3V)
100
DIR_DO
I
Serial data input from the digital audio interface receiver
STR-CT550WT
47
MAIN  BOARD  IC5001  ADSST-AVR-3010 (DSP)
Pin No.
Pin Name
I/O
Description
1
SDDQM
O
DQM data mask terminal    Not used
2
MS0
O
Memory select terminal    Not used
3
SDCKE
O
SDRAM clock enable terminal    Not used
4
VDD_INT
-
Power supply terminal (+1.2V) (for core)
5
CLK_CFG1
I
Clock frequency setting terminal     Fixed at “L” in this unit
6
ADDR0
O
Address signal output terminal    Not used
7
BOOT_CFG0
I
Boot mode selection signal input terminal    Fixed at “H” in this unit
8
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
9 to 13
ADDR1 to ADDR5
O
Address signal output terminal    Not used
14
BOOT_CFG1
I
Boot mode selection signal input terminal
15
GND
-
Ground terminal
16, 17
ADDR6, ADDR7
O
Address signal output terminal   Not used
18, 19
N. A
-
Not used
20, 21
ADDR8, ADDR9
O
Address signal output terminal   Not used
22
CLK_CFG0
I
Clock frequency setting terminal     Fixed at “L” in this unit
23
VDD_INT
-
Power supply terminal (+1.2V) (for core)
24
CLKIN
I
System clock input terminal (25 MHz)
25
XTAL2
O
System clock output terminal (25 MHz)
26
ADDR10
O
Address signal output terminal    Not used
27
SDA10
O
Not used
28
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
29
VDD_INT
-
Power supply terminal (+1.2V) (for core)
30 to 33
ADDR11, ADDR12, 
ADDR17, ADDR13
O
Address signal output terminal    Not used
34
VDD_INT
-
Power supply terminal (+1.2V) (for core)
35
ADDR18
O
Address signal output terminal    Not used
36
RESETOUT/
RUNRSTIN
I/O
Reset signal output terminal/Running reset signal input terminal    Not used
37
VDD_INT
-
Power supply terminal (+1.2V) (for core)
38
MOSI
I
Serial data input from the system controller
39
MISO
O
Serial data output to the system controller
40
SPICLK
I
Serial data transfer clock signal input from the system controller
41
VDD_INT
-
Power supply terminal (+1.2V) (for core)
42
DPI_P05
I
Chip select signal input from the system controller
43
DSP_CS
I
Chip select signal input from the system controller
44
MD
-
Not used
45
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
46
NC
-
Not used
47
RESET_MAIN
I
Reset signal input terminal    Not used
48
VDD_INT
-
Power supply terminal (+1.2V) (for core)
49
UART_OUT
O
Serial data output to the system controller
50
UART_IN
I
Serial data input from the system controller
51
LED
O
Not used
52 to 56
NC
-
Not used
57
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
58 to 61
NC
-
Not used
62
VDD_INT
-
Power supply terminal (+1.2V) (for core)
63, 64
NC
-
Not used
65
VDD_INT
-
Power supply terminal (+1.2V) (for core)
66, 67
NC
-
Not used
68
VDD_INT
-
Power supply terminal (+1.2V) (for core)
69
NC
-
Not used
70
WDTRSTO
O
Watchdog timer reset out terminal    Not used
71
NC
-
Not used
72
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
73
SL/SR_OUT
O
Audio signal output terminal    Not used
74
SL/SR_IN
I
Audio signal input from the digital audio interface receiver
75
BCLK_IN
I
Bit clock signal input from the digital audio interface receiver
STR-CT550WT
48
Pin No.
Pin Name
I/O
Description
76
OPTION_L/
OPTION_R_OUT
O
Audio signal output terminal    Not used
77
FRONTHI_L/R_OUT
-
Not used
78
VDD_INT
-
Power supply terminal (+1.2V) (for core)
79 to 83
NC
-
Not used
84
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
85
VDD_INT
-
Power supply terminal (+1.2V) (for core)
86
L/R_OUT
O
Audio signal output terminal
87
MID/SW2_OUT
O
Not used
88
SBL/SBR_OUT
O
Not used
89
ZONE_L/R
O
Not used
90
VDD_INT
-
Power supply terminal (+1.2V) (for core)
91
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
92
MCLK_IN
I
Master clock signal input from the digital audio interface receiver
93
VDD_INT
-
Power supply terminal (+1.2V) (for core)
94
C/SW1_OUT
O
Audio signal output terminal
95
C/SW_IN
I
Audio signal input from the digital audio interface receiver
96
A/D_2CH
I
Audio signal input from the digital audio interface receiver
97
LRCLK_IN
I
L/R sampling clock signal input from the digital audio interface receiver
98
BCLK_OUT
O
Bit clock signal output to the stream processor
99
LRCLK_OUT
O
L/R sampling clock signal output to the stream processor
100
L/R_IN
I
Audio signal input from the digital audio interface receiver
101
SBL/SBR_IN
I
Audio signal input from the digital audio interface receiver
102
VDD_INT
-
Power supply terminal (+1.2V) (for core)
103
DIR_IN
I
Audio signal input from the digital audio interface receiver
104
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
105
VDD_INT
-
Power supply terminal (+1.2V) (for core)
106
BOOT_CFG2
I
Boot mode selection signal input terminal    Fixed at “L” in this unit
107
VDD_INT
-
Power supply terminal (+1.2V) (for core)
108
AMI_ACK
I
Memory acknowledge terminal    Not used
109
GND
-
Ground terminal
110
THD_M
O
Thermal diode cathode output terminal    Not used
111
THD_P
I
Thermal diode anode input terminal    Not used
112
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
113, 114
VDD_INT
-
Power supply terminal (+1.2V) (for core)
115
MS1
O
Memory select terminal    Not used
116
VDD_INT
-
Power supply terminal (+1.2V) (for core)
117
WDT_CLKO
O
Watchdog resonator pad output terminal    Not used
118
WDT_CLKIN
I
Watchdog timer clock input terminal    Fixed at “L” in this unit
119
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
120 to 
122
ADDR23 to ADDR21
O
Address signal output terminal   Not used
123
VDD_INT
-
Power supply terminal (+1.2V) (for core)
124, 125
ADDR20, ADDR19
O
Address signal output terminal   Not used
126
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
127, 128
ADDR16, ADDR15
O
Address signal output terminal   Not used
129
VDD_INT
-
Power supply terminal (+1.2V) (for core)
130
ADDR14
O
Address signal output terminal   Not used
131
AMI_WR
O
AMI port write enable terminal    Not used
132
AMI_RD
O
AMI port read enable terminal    Not used
133
VDD_INT
-
Power supply terminal (+1.2V) (for core)
134
IRQ/GPIO
O
Interrupt request signal output to the system controller 
135
FLAG1
I
Error signal input terminal
136
FLAG2
I
Non-PCM audio signal input terminal
137
MLBCLK
I
Not used
138
FLAG3
I
Not used
139
MLBDAT
I
Not used
140
MLBDO
I
Not used
141
VDD_EXT
-
Power supply terminal (+3.3V) (for I/O)
142
MLBSIG
I
Not used
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