Sony HT-BE1 / SA-WBE1 / SS-BE1 Service Manual ▷ View online
9
HT-BE1/SA-WBE1/SS-BE1
58
BVDD
—
Power supply pin (+3.3 V)
59
BVSS
—
Ground
60, 61
NC
—
Not used. (Open)
62
READY-H
O
Power supply (ready) output
63
USB-PLYSCK
I
USB play/idle decision input
64 to 66
NC
—
Not used. (Open)
67
USB-H
O
USB/analog select output
68
VOL-STB
O
Latch output for volume control.
69
VOL-CLK
O
Clock output output for volume control.
70
VOL-DATA
O
Data output for volume control.
71
NC
—
Not used. (Open)
72
READY-H
O
Ready LED ON/OFF control output (ready mode: red LED light on)
73
NC
—
Not used. (Open)
74
AVDD
—
Analog power supply pin (+5 V)
75
AVSS
—
Analog ground
76
AVREF
—
Analog reference voltage pin (+5 V)
77 to 80
NC
—
Not used. (Fixed at H)
81
AUDIO DEC
I
Auto power ON/OFF level check input
82
KEY1
I
Key AD value input
83
ENA
I
Encoder A input
84
ENB
I
Encoder B input
85
DIGITAL DEC
I
Level decision input from DIR.
86 to 88
NC
—
Not used. (Fixed at H)
89
NC
—
Not used. (Open)
90
STOP
I
Stop mode check signal input
91
SIRCS
I
SIRCS signal input
92
RDS-DATA
I
Not used. (Open)
93
P-WAKE
I
Interruption signal input from STOP mode.
94 to 96
NC
—
Not used. (Open)
97
IN
I
µ-com programming serial in input
98
CO-S/MUTE
O
Soft mute control output for MAC.
99
CO-PD
O
Soft reset control output for MAC
100
CO-CS
O
Chip select output for MAC.
Pin No.
Pin Name
I/O
Pin Description
10
HT-BE1/SA-WBE1/SS-BE1
1
VSS
—
Ground
2
XRST
I
Reset signal input from system controller.
3
EXTIN
I
Not used. (Connected to ground)
4
FS2
I
Not used. (Connected to ground)
5
VDDI
I
Power supply pin (+2.4 V)
6
FS1
I
Not used. (Connected to ground)
7
PLOCK
O
Internal PLL lock signal output for system controller.
8
VSS
—
Ground
9
MCLK1
I
Clock signal input (13.5 MHz)
10
VDDI
I
Power supply pin (+2.4 V)
11
VSS
—
Ground
12
MCLK2
O
Clock signal output (13.5 MHz)
13
MS
I
Switching signal input of master/slave operation. (Fixed at L : internal clock)
14
SCKOUT
O
Internal system clock signal output
15
LRCKI1
I
Not used. (open)
16
VDDE
I
Power supply pin (+3.3 V)
17
BCKI1
I
Not used. (open)
18
SDI1
I
Audio IF data input
19
LRCKO
O
Sampling clock output for digital audio serial data
20
BCKO
O
Bit clock output for digital audio serial data
21
VSS
—
Ground
22
KFSIO
I/O
Audio clock signal (384fs/256fs) input/output
23 to 25
SDO1 to SDO3
O
Digital audio serial data output
26
SDO4
O
Audio IF serial output (Not used. (open))
27
SPDIF
O
Not used. (open)
28
LRCKI2
I
Sampling clock input from audio serial data.
29
BCKI2
I
Bit clock input from audio serial data.
30
SDI2
I
Digital audio data input
31
VSS
—
Ground
32
HACN
O
Acknowledge signal output for system controller.
33
HDIN
I
Serial data input from system controller.
34
HCLK
I
Clock input from system controller.
35
HDOUT
O
Serial data output for system controller.
36
HCS
I
Chip select input from system controller.
37
SDCLK
O
Not used. (open)
38
CLKEN
O
Not used. (open)
39
RAS
O
Not used. (open)
40
VDDI
I
Power supply pin (+2.4 V)
41
VSS
—
Ground
42
CAS
O
Not used. (open)
43
DQM/OE0
O
Not used. (open)
44
CS0
O
External memory chip select output (SRAM) (Not used. (open))
45
WE0
O
SRAM write enable output (Not used. (open))
46
VDDE
I
Power supply pin (+3.3 V)
47
WMD1
I
Not used. (Fixed at L)
48
VSS
—
Ground
49
WMD0
I
Not used. (Fixed at L)
50
PAGE2
O
Not used. (open)
51
VSS
—
Ground
52
PAGE1
O
External memory page switching signal output (Not used. (open))
53
PAGE0
O
External memory page switching signal output (Not used. (open))
54
BOOT
I
Not used. (open)
• IC802 CXD9617R (DSP)
Pin No.
Pin Name
I/O
Pin Description
11
11
HT-BE1/SA-WBE1/SS-BE1
Note on Schematic Diagram:
• All capacitors are in µF unless otherwise noted. (p: pF)
• All capacitors are in µF unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
and tantalums.
• All resistors are in
Ω
and
1
/
4
W or less unless otherwise
specified.
•
2
: nonflammable resistor.
•
C
: panel designation.
Note:
The components identi-
fied by mark
The components identi-
fied by mark
0
or dotted
line with mark
0
are criti-
cal for safety.
Replace only with part
number specified.
Replace only with part
number specified.
Note:
Les composants identifiés par
une marque
Les composants identifiés par
une marque
0
sont critiques
pour la sécurité.
Ne les remplacer que par une
piéce portant le numéro
spécifié.
Ne les remplacer que par une
piéce portant le numéro
spécifié.
•
A
: B+ Line.
• Voltage is dc with respect to ground under no-signal
(detuned) condition.
• Voltages are taken with a VOM (Input impedance 10 M
Ω
).
Voltage variations may be noted due to normal produc-
tion tolerances.
tion tolerances.
• Signal path.
F
: LINE
c
: DIGITAL AUDIO (OPTICAL)
J
: DIGITAL AUDIO (COAXIAL)
• Abbreviation
CND : Canadian model.
SP
SP
: Singapore model.
MY
: Malaysia model.
MX
: Mexican model.
• (
) : Page of Service Manual.
((
)) : Page of Supplement-1.
Note on Printed Wiring Boards:
• X
: parts extracted from the component side.
•
: Pattern from the side which enables seeing.
• Abbreviation
CND : Canadian model.
SP
SP
: Singapore model.
MY
: Malaysia model.
MX
: Mexican model.
• (
) : Page of Service Manual.
((
)) : Page of Supplement-1.
55
BTACT
O
Not used. (open)
56
BST
I
Boot stop signal input from system controller.
57
MOD1
I
Operation mode signal input (Fixed at H : 256fs)
58
MOD0
I
Operation mode signal input (Fixed at L : single chip mode)
59
EXLOCK
I
Lock signal input
60
VDDI
I
Power supply pin (+2.4 V)
61
VSS
—
Ground
62 to 66
A17 to A13
O
External memory address output (SRAM) (Not used. (open))
67
GP10
O
Connected to LRCKO
68
GP9
O
Decode signal output for system controller.
69
GP8
I
Audio signal input from DIR.
70
VDDI
I
Power supply pin (+2.4 V)
71
VSS
—
Ground
72 to 75
D15/GP7 to D12/GP4
I/O
External memory data input/output (general port) (Not used. (open))
76
VDDE
I
Power supply pin (+3.3 V)
77 to 80
D11/GP3 to D8/GP0
I/O
External memory data input/output (general port) (Not used. (open))
81
VSS
—
Ground
82
A9
O
External memory address output (SRAM) (Not used. (open))
83 to 85
A12 to A10
O
External memory address output (SRAM) (Not used. (open))
86
TDO
O
Not used. (open)
87
TMS
I
Not used. (open)
88
XTRST
I
Not used. (open)
89
TCK
I
Not used. (open)
90
TDI
I
Not used. (open)
91
VSS
—
Ground
92 to 97
A8 to A3
O
External memory address output (SRAM) (Not used. (open))
98, 99
D7, D6
I/O
External memory data input/output (SRAM) (Not used. (open))
100
VDDI
I
Power supply pin (+2.4 V)
101
VSS
—
Ground
102 to 105
D5 to D2
I/O
External memory data input/output (SRAM) (Not used. (open))
106
VDDE
I
Power supply pin (+3.3 V)
107, 108
D1, D0
I/O
External memory data input/output (SRAM) (Not used. (open))
109, 110
A2, A1
O
External memory address output (SRAM) (Not used. (open))
111
VSS
—
Ground
112
A0
O
External memory address output (SRAM) (Not used. (open))
113
PM
I
PLL initialization input from system controller.
114, 115
SDI3, SDI4
I
Not used. (open)
116
SYNC
I
Sync/async selection input (Fixed at H : async)
117 to 119
VSS
—
Ground
120
VDDI
I
Power supply pin (+2.4 V)
Pin No.
Pin Name
I/O
Pin Description
• Waveforms
1
IC501
wk
(XT0)
1V/div 50nsec/div
12.0MHz
2
IC803
wa
(XOUT)
1V/div 50nsec/div
12.288MHz
3
IC801
ek
(X2)
1V/div 20nsec/div
4
IC802
qs
(MCLK2)
1V/div 50nsec/div
16.0MHz
13.5MHz
5
IC802
qf
(SCKOUT)
1V/div 50nsec/div
13.5MHz
3.0Vp-p
3.5Vp-p
2.6Vp-p
3.1Vp-p
4.0Vp-p
Ver. 1.3
12
12
HT-BE1/SA-WBE1/SS-BE1
30
AUDIO
5V
AVDD
AMP
IC507
INPUT SELECT
IC502
AUDIO DETECT
IC505
DSI1
SDTI1
L-OUT
SL-OUT
C-OUT
SW-OUT
SDO1
SDTO
29
9
18
GP8
AUDIO 24
69
KFSIO
CKOUT 13
22
BCKI2
BCK 14
29
LRCKI2
LRCK 15
28
SDI2
DATA
SCKOUT
MCLKI 39
14
23
6
SDTI2
SDO2 24
7
SDTI3
SDO3 25
8
27
GP10 67
LRCK
LRCKO 19
5
BCLK
BCKO 20
4
17
X804
13.5MHz
MCLK1 9
MCLK2 12
68 56
2 113
36
35 7
32
15
16
23
11 12
13
6 17
14
EXLOCK
ERROR
1
8
19
7
24
22
20
38
37
36
35
33
48
17
3
43
42
41
99
98
1
2
100
34
DAC
DAC
DAC
DAC
25
23
24
AUDIO
I/F
(2/2)
INPUT
DATA
DEMODULATOR
Pa,Pb DETECTION
LOCK
DETECTION
MICROPROCESSOR
I/F
C bit DETECTION
34
59
HDIN
33
HCLK
34
16
30
DIGITAL
COAXIAL
OPTICAL
USB
J501
OUT
OPTICAL
RECEIVER
IC503
IC509
DIGITAL AUDIO
I/F RECEIVER
IC803
J502
2
3
WAVE
SHAPER
6
7
2
1
D5V
D510
READY
D5V
D 5.6V
(SW)
D 5.6V
(UNSW)
+2.5V
VDDI
+3.3V
VDDE
READY
+3.3V
VDD
R-CH
LIN-
LIN+
LPF
AUDIO
I/F
(1/2)
MULTI-CHANNEL
AUDIO CODEC
IC804
DSP
IC802
L
SL
C
SW
PD
S/M
CDT1
CCLK
CS
CO-PD
21
VPP
97
IN
X2
X1
CO-S/MUTE
CO-DI
CO-CLK
CO-CS
RESET
STOP
AVREF
DSP-GP9
DIR-XMODE
18
DIR-ERR
DSP-HACN
DSP-BST
DSP-CS
DSP-RST
DSP-PLOCK
DSP-PM
DSP-DO
GP9
HACN
BST
HCS
XRST
PLOCK
PM
HDOUT
DIG-CLK
81
AUDIO DEC
67
USB-H
DIR-CE
DIG-DI
DIRDO
DIR-AD
DIR-XST
CL
CE
DI
DO
BPSYNC
XMODE
XSTATE
D802
D803
VDD
D812
D811
D811
3
4
2
1
LPF
IC506
X803
12.288MHz
21
22
XOUT
XIN
X801
16MHz
39
38
63 USB-PLYSCK
R-CH
VOUTL
VOUTR
PLYBCK
D804
SYSTEM
CONTROLLER
IC801 (1/2)
POWER
SECTION
A
AUDIO IN
ADC
DIN0
DIN1
12
6
2
6
1
7
8
10
9
8
23
19
10
7
6
1
28
90
1
2
2
1
76
11
MUTE
Q504
RESET
Q801
USB
I/F
CRYSTAL
OSC
DAC
BIAS
SWITCH
Q505
XT0
XT1
D+
D-
VBUS
X501
12MHz
Q507
OSC
SWITCH
+2.5V
REG
IC807
+2.5V
3
2
+3.3V
REG
IC808
+3.3V
IN
OUT
2PIN
CLK
VPP
RESET
8
7
6
5
4
3
CN802
(PROGRAMMING)
RESET
IC806
Q502
Q501
L
R
-1
-2
-3
Q506
USB
BUS
BUS
DETECT
VBUS
D-
D+
GND
1
2
3
4
USB INTERFACE,
D/A CONVERTER
D/A CONVERTER
IC501
D507
D506
R-CH
EXCEPT
US,CND,MX
MODEL
D504
• Signal path
: LINE
: DIGITAL AUDIO (COAXIAL)
: DIGITAL AUDIO (OPTICAL)
• R-ch is omitted due to
same as L-ch.
same as L-ch.
• Abbreviation
CND: Canadian model
MX : Mexican model
4-2. BLOCK DIAGRAM — MAIN SECTION —
(Page 13)
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