Sony HT-BE1 / SA-WBE1 / SS-BE1 Service Manual ▷ View online
7
HT-BE1/SA-WBE1/SS-BE1
3-4. MAIN BOARD
2
BVTP 3x10
5
BVTP 3x10
6
BVTP 3x10
4
CN421
8
DC fan (FAN901)
9
MAIN board
3
BVTP 3x10
heat sink
7
BTP 3x25
1
CN382
8
HT-BE1/SA-WBE1/SS-BE1
1
LRSY
I
CD L/R clock input
1
CO-DI
O
Data output for MAC.
2
CO-CLK
O
Clock output for MAC.
3
U L/OTHER H
I
Destination setting input (L: US, Canadian, Mexican model, H: Except US, Canadian,
Mexican model)
4
USB L/OTHER H
I
USB setting input (Fixed at L)
5
NC
—
Not used. (Open)
6
DSP-DO
O
Serial data output for DSP.
7
DIG-DI
I
Serial data input from DSP.
8
DIG-CLK
O
Clock output for DSP.
9
EVDD
—
Power supply pin (+3.3 V)
10
EVSS
—
Ground
11
DSP-RST
O
Reset signal output for DSP. (L: active)
12
DSP-PM
O
PLL initialization output for DSP.
13
DSP-CS
O
Chip select output for DSP.
14
DSP-HACN
I
Acknowledge signal input from DSP.
15
DSP-BST
O
Boot stop signal output for DSP.
16
DSP-GP9
I
Decode signal input from DSP.
17
DSP-PLOCK
I
Internal PLL lock signal input from DSP.
18
DIR-ERR
I
PLL lock signal input from DIR.
19
DIR-CE
O
Chip enable signal output for DIR.
20
DIR-XST
I
Reset signal input from DIR.
21
VPP
—
Programming power supply pin
22
DIR-AD
O
Serial data output for DIR.
23
DIR-XMODE
I
System reset signal input from DIR.
24
DIRDO
I
Serial data input from DIR.
25, 26
NC
—
Not used. (Open)
27
MUTE-FL,FR
O
Amplifier mute (FL, FR) output
28
MUTE-SL,SR,C
O
Amplifier mute (SL, SR, C) output
29
MUTE-SW
O
Amplifier mute (SW) output
30 to 33
NC
—
Not used. (Open)
34
RESET
I
µ-com reset signal input
35
XT1
I
Not used. (Fixed at L)
36
XT2
O
Not used. (Open)
37
NC
—
Not used. (Connected to capacitor)
38
X2
O
Main clock signal output (16 MHz)
39
X1
I
Main clock signal input (16 MHz)
40
VSS
—
Ground
41
VDD
—
Power supply pin (+5 V)
42, 43
NC
—
Not used. (Open)
44
AMP-MUTE
O
Amplifier mute output
45
NC
—
Not used. (Open)
46
P-CONT
I
Power control signal input
47 to 50
NC
—
Not used. (Open)
51
DISC
I
Not used. (Fixed at L)
52
NC
—
Not used. (Open)
53
LCD-CLK
O
Clock output for LCD driver.
54
LCD-DATA
O
Serial data output for LCD driver.
55
LCD-CS
O
Chip select output for LCD driver.
56
LCD-C/D
O
Latch output for LCD driver.
57
LED-CLR
—
Not used. (Open)
SECTION 4
DIAGRAMS
4-1. IC PIN DESCRIPTIONS
• IC801 µPD703033A (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Pin Description
9
HT-BE1/SA-WBE1/SS-BE1
58
BVDD
—
Power supply pin (+3.3 V)
59
BVSS
—
Ground
60, 61
NC
—
Not used. (Open)
62
READY-H
O
Power supply (ready) output
63
USB-PLYSCK
I
USB play/idle decision input
64 to 66
NC
—
Not used. (Open)
67
USB-H
O
USB/analog select output
68
VOL-STB
O
Latch output for volume control.
69
VOL-CLK
O
Clock output output for volume control.
70
VOL-DATA
O
Data output for volume control.
71
NC
—
Not used. (Open)
72
READY-H
O
Ready LED ON/OFF control output (ready mode: red LED light on)
73
NC
—
Not used. (Open)
74
AVDD
—
Analog power supply pin (+5 V)
75
AVSS
—
Analog ground
76
AVREF
—
Analog reference voltage pin (+5 V)
77 to 80
NC
—
Not used. (Fixed at H)
81
AUDIO DEC
I
Auto power ON/OFF level check input
82
KEY1
I
Key AD value input
83
ENA
I
Encoder A input
84
ENB
I
Encoder B input
85
DIGITAL DEC
I
Level decision input from DIR.
86 to 88
NC
—
Not used. (Fixed at H)
89
NC
—
Not used. (Open)
90
STOP
I
Stop mode check signal input
91
SIRCS
I
SIRCS signal input
92
RDS-DATA
I
Not used. (Open)
93
P-WAKE
I
Interruption signal input from STOP mode.
94 to 96
NC
—
Not used. (Open)
97
IN
I
µ-com programming serial in input
98
CO-S/MUTE
O
Soft mute control output for MAC.
99
CO-PD
O
Soft reset control output for MAC
100
CO-CS
O
Chip select output for MAC.
Pin No.
Pin Name
I/O
Pin Description
10
HT-BE1/SA-WBE1/SS-BE1
1
VSS
—
Ground
2
XRST
I
Reset signal input from system controller.
3
EXTIN
I
Not used. (Connected to ground)
4
FS2
I
Not used. (Connected to ground)
5
VDDI
I
Power supply pin (+2.4 V)
6
FS1
I
Not used. (Connected to ground)
7
PLOCK
O
Internal PLL lock signal output for system controller.
8
VSS
—
Ground
9
MCLK1
I
Clock signal input (13.5 MHz)
10
VDDI
I
Power supply pin (+2.4 V)
11
VSS
—
Ground
12
MCLK2
O
Clock signal output (13.5 MHz)
13
MS
I
Switching signal input of master/slave operation. (Fixed at L : internal clock)
14
SCKOUT
O
Internal system clock signal output
15
LRCKI1
I
Not used. (open)
16
VDDE
I
Power supply pin (+3.3 V)
17
BCKI1
I
Not used. (open)
18
SDI1
I
Audio IF data input
19
LRCKO
O
Sampling clock output for digital audio serial data
20
BCKO
O
Bit clock output for digital audio serial data
21
VSS
—
Ground
22
KFSIO
I/O
Audio clock signal (384fs/256fs) input/output
23 to 25
SDO1 to SDO3
O
Digital audio serial data output
26
SDO4
O
Audio IF serial output (Not used. (open))
27
SPDIF
O
Not used. (open)
28
LRCKI2
I
Sampling clock input from audio serial data.
29
BCKI2
I
Bit clock input from audio serial data.
30
SDI2
I
Digital audio data input
31
VSS
—
Ground
32
HACN
O
Acknowledge signal output for system controller.
33
HDIN
I
Serial data input from system controller.
34
HCLK
I
Clock input from system controller.
35
HDOUT
O
Serial data output for system controller.
36
HCS
I
Chip select input from system controller.
37
SDCLK
O
Not used. (open)
38
CLKEN
O
Not used. (open)
39
RAS
O
Not used. (open)
40
VDDI
I
Power supply pin (+2.4 V)
41
VSS
—
Ground
42
CAS
O
Not used. (open)
43
DQM/OE0
O
Not used. (open)
44
CS0
O
External memory chip select output (SRAM) (Not used. (open))
45
WE0
O
SRAM write enable output (Not used. (open))
46
VDDE
I
Power supply pin (+3.3 V)
47
WMD1
I
Not used. (Fixed at L)
48
VSS
—
Ground
49
WMD0
I
Not used. (Fixed at L)
50
PAGE2
O
Not used. (open)
51
VSS
—
Ground
52
PAGE1
O
External memory page switching signal output (Not used. (open))
53
PAGE0
O
External memory page switching signal output (Not used. (open))
54
BOOT
I
Not used. (open)
• IC802 CXD9617R (DSP)
Pin No.
Pin Name
I/O
Pin Description
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