Sony HMD-M11 Service Manual ▷ View online
– 89 –
DIGITAL BOARD IC100 RU8X12MF-0012 (MECHANISM CONTROLLER)
Pin No. Pin Name
I / O
Function
1
DAOUT0
O
Output terminal for the test C1 is output when test mode
2
DAOUT1
O
Output terminal for the test ADER is output when test mode
3
KEY0
I
4
KEY1
I
Key input terminal Not used (fixed at “H”)
5
KEY2
I
6
CHACK-IN
I
Detection input from the disc chucking-in detect switch (S685) “L”: chucking
7
PACK-IN
I
Detection input from the disc detect switch Not used (fixed at “H”)
8
PACK-OUT
I
Detection input from the loading-out detect switch (S686) “L” at a load-out position, others: “H”
9
—
I
Not used (fixed at “L”)
10
—
I
Not used (fixed at “L”)
11
AVSS
—
Ground terminal
12
XINT
I
Interrupt status input from the CXD2650R (IC121)
13
PDOWN
I
Power down detection signal input terminal “L”: power down, normally: “H”
14
—
I
Not used (fixed at “L”)
15
SQSY
I
Subcode Q sync (SCOR) input from the CXD2650R (IC121)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
16
DQSY
I
Digital In U-bit CD format subcode Q sync (SCOR) input from the CXD2650R (IC121)
“L” is input every 13.3 msec Almost all, “H” is input
“L” is input every 13.3 msec Almost all, “H” is input
17
—
I
18
—
I
Not used (fixed at “L”)
19
—
I
20
SYS-RST
I
System reset signal input from the master controller (IC700) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
21
TEST
I
Input terminal for the test Fixed at “L” in this set
22
+3.3V
—
Power supply terminal (+3.3V)
23
VBAT
I
Power supply terminal for the backup (for internal RAM)
24
XOUT-T
O
Sub system clock output terminal (32.768 kHz)
25
XIN-T
I
Sub system clock input terminal (32.768 kHz)
26
GND
—
Ground terminal
27
XOUT
O
Main system clock output terminal (12 MHz)
28
XIN
I
Main system clock input terminal (12 MHz)
29
EXMEM
I
Selected terminal for the RAM device
“L”: used for internal RAM, “H”: used for external RAM device (fixed at “L” in this set)
“L”: used for internal RAM, “H”: used for external RAM device (fixed at “L” in this set)
30
S1
O
System clock output terminal Not used (open)
31
—
I
Not used (fixed at “L”)
32
SENS
I
Internal status (SENSE) input from the CXD2650R (IC121)
33
SHOCK
I
Track jump detection signal input from the CXD2650R (IC121)
34
—
I
Not used (fixed at “L”)
35
—
I
Not used (fixed at “L”)
36
STB
O
Strobe signal output to the main power supply circuit “H”: power on, “L”: standby mode
37
REC P
I
Detection input from the recording position detect switch (S688) “L” active
38
PB P
I
Detection input from the playback position detect switch (S687) “L” active
39
LD LOW
O
Loading motor voltage control signal output to the loading motor driver (IC361)
40
—
O
Not used (open)
41
MNT2
I
Monitor 2 signal input from the CXD2650R (IC121)
42
MNT3
I
Monitor 3 signal input from the CXD2650R (IC121)
– 90 –
Pin No. Pin Name
I / O
Function
43
LED0
O
LED drive signal output terminal Not used (open)
44
—
I
Not used (fixed at “L”)
45
—
I
Not used (fixed at “L”)
46
RST-LOW
O
Output of signal to place the reset in “L” status after a backup processing is finished
47
GND
—
Ground terminal
48
+3.3V
—
Power supply terminal (+3.3V)
49
SNG/CHG
I
Input terminal for setting mini-disc single mode or changer mode
“L”: mini-disc single mode, “H”: changer mode (fixed at “L” in this set)
“L”: mini-disc single mode, “H”: changer mode (fixed at “L” in this set)
50
JOG1
I
JOG dial pulse input of the rotary encoder Not used (fixed at “L”)
51
JOG0
I
JOG dial pulse input of the rotary encoder Not used (fixed at “L”)
52
SDA
I/O
Two-way data bus for the EEPROM (IC171)
53
SCL
O
Clock signal output to the EEPROM (IC171)
54
—
I
55
—
I
Not used (fixed at “L”)
56
—
I
57
RXD
I
UART data input from the master controller (IC700)
58
TXD
O
UART data output to the master controller (IC700)
59
RTS
O
Output of signal to inhibit data transmission to the master controller (IC700)
60
CTS
I
Input of signal to reject data reception from the master controller (IC700)
61
—
I
Not used (fixed at “L”)
62
—
I
Not used (fixed at “L”)
63
CLKSET0
I
Clock destination selected terminal (fixed at “L” in this set)
64
CLKSET1
I
Clock destination selected terminal (fixed at “L” in this set)
65
GND
—
Ground terminal
66
+3.3V
—
Power supply terminal (+3.3V)
67
SCLK
O
Serial clock signal output to the CXD2650R (IC121) and A/D, D/A converter (IC202)
68
SWDT
O
Writing data output to the CXD2650R (IC121) and A/D, D/A converter (IC202)
69
SRDT
I
Reading data input from the CXD2650R (IC121)
70
EMP
O
Emphasis control signal output terminal when recording mode Not used (open)
71
SCK1
O
Serial clock signal output for the display Not used (open)
72
SOUT1
O
Serial data output for the display Not used (open)
73
SIN1
O
Chip select signal output for the display Not used (open)
74
CSB
I
Not used (fixed at “H”)
75
LDON
O
Laser diode on/off control signal output to the automatic power control circuit “H”: laser on
76
PIT/GRV
O
Pit/groove detection signal output terminal
“H” is output for the playback only disc or TOC area Not used (open)
“H” is output for the playback only disc or TOC area Not used (open)
77
FOK
I
Focus OK signal input from the CXD2650R (IC121) “H” is input when focus is on
78
—
O
Not used (open)
79
LOCK
O
Lock signal output terminal Not used (open)
80
WRPWR
O
Laser power select signal output to the CXD2650R (IC121)
“H”: recording mode, “L”: playback mode
“H”: recording mode, “L”: playback mode
81
DIG-RST
O
Reset signal output to the CXD2650R (IC121) and BH6511FS (IC152) “L”: reset
82
—
O
Not used (open)
83
DA-RST
O
Reset signal output to the A/D, D/A converter (IC202) “L”: reset
84
DSEL-A
O
Not used (open)
85
DSEL-B
O
Not used (open)
– 91 –
Pin No. Pin Name
I / O
Function
Laser modulation select signal output
Playback power: “L”, Stop: “H”,
Recording power:
86
MOD
O
87
REC/PB
O
Not used (open)
88
—
O
Not used (open)
89
SCTX
O
Recording data output enable signal output to the CXD2650R (IC121)
Writing data transmission timing output (Also serves as the magnetic head on/off output)
Writing data transmission timing output (Also serves as the magnetic head on/off output)
90
XLATCH
O
Serial latch signal output to the CXD2650R (IC121) and A/D, D/A converter (IC202)
91
—
O
Not used (open)
92
—
O
Not used (open)
93
AMUTE
O
Mute control signal output terminal Not used (open)
94
LDOUT
O
Motor control signal output to the loading motor driver (IC361) *1
95
LDIN
O
Motor control signal output to the loading motor driver (IC361) *1
96
LIMIT-IN
I
Detection input from the sled limit-in detect switch (S681)
The optical pick-up is inner position when “L”
The optical pick-up is inner position when “L”
97
PROTECT
I
Rec-proof claw detect input from the protect detect switch (S683) “H”: write protect
98
REFLECT
I
Detection input from the disc reflection rate detect switch (S682)
“L”: high reflection rate disc, “H”: low reflection rate disc
“L”: high reflection rate disc, “H”: low reflection rate disc
99
GND
—
Ground terminal
100
+3.3V
—
Power supply terminal (+3.3V)
2 sec
0.5 sec
*1 Loading Motor Control
I
N
OUT
BR AKE
RUN IDLE
LDIN ( pin
(∞)
“H”
“L”
“H”
“L”
LDOUT ( pin
(¢)
“L”
“H”
“H”
“L”
Terminal
Operation
– 92 –
DIGITAL BOARD IC202 CXD8607N (A/D, D/A CONVERTER)
Pin No. Pin Name
I / O
Function
1
INRP
I
R-ch analog signal (+) input terminal
2
INRM
I
R-ch analog signal (–) input terminal
3
REFI
I
Reference voltage (+3.3V) input terminal (for A/D converter section)
4
AVDD
—
Power supply terminal (+5V) (for A/D converter section, analog system)
5
AVSS
—
Ground terminal (for A/D converter section, analog system)
6
APD
I
Power down detection input of the A/D converter section (for analog section) “L”: power down
7
NU
—
Not used (open)
8
NU
—
Not used (open)
9
TEST1
I
Input terminal for the test (fixed at “L”)
10
LRCK1
I
L/R clock signal (44.1 kHz) input from the CXD2650R (IC121) (for A/D converter section)
11
BCK1
I
Bit clock signal (2.8224 MHz) input from the CXD2650R (IC121) (for A/D converter section)
12
ADDT
O
Recording data output terminal
13
V35A
—
Power supply terminal (+3.3V) (for analog system)
14
VSS1
—
Ground terminal (for A/D converter section, digital system)
15
MCKI
I
Master clock (256Fs=11.2896 MHz) input of the A/D converter section
16
DPD
I
Reset signal input from the mechanism controller (IC100) Reset signal is used as a detection
signal of power down to A/D converter (digital section) “L”: reset (power down)
signal of power down to A/D converter (digital section) “L”: reset (power down)
17
VSS2
—
Ground terminal (for D/A converter section, digital system)
18
RES
I
Reset signal input from the mechanism controller (IC100)
Reset signal is used as a initialize signal to D/A converter section “L”: reset (initialize)
Reset signal is used as a initialize signal to D/A converter section “L”: reset (initialize)
19
MODE
I
Writing data input from the mechanism controller (IC100)
20
SHIFT
I
Serial clock signal input from the mechanism controller (IC100)
21
XLATCH
I
Serial latch signal input from the mechanism controller (IC100)
22
256CK
O
256Fs (11.2896 MHz) clock signal output terminal
23
V35D
—
Power supply terminal (+3.3V) (for digital system)
24
VSS2
—
Ground terminal (for D/A converter section, digital system)
25
512FS
O
512Fs (22.5792 MHz) clock signal output to the CXD2650R (IC121)
26
BCK2
I
Bit clock signal (2.8224 MHz) input from the CXD2650R (IC121) (for D/A converter section)
27
DADT
I
Playback data input terminal
28
LRCK2
I
L/R clock signal (44.1 kHz) input from the CXD2650R (IC121) (for D/A converter section)
29
VDD2
—
Power supply terminal (+5V) (for D/A converter section, digital system)
30
R1
O
R-ch PLM signal 1 output terminal
31
AVDDR
—
Power supply terminal (+5V) (for R-ch side D/A converter section, analog system)
32
R2
O
R-ch PLM signal 2 output terminal
33
AVSSR
—
Ground terminal (for R-ch side D/A converter section, analog system)
34
XVDD
—
Power supply terminal (+5V) (for X’tal system)
35
XOUT
O
System clock output terminal (22 MHz)
36
XIN
I
System clock input terminal (22 MHz)
37
XVSS
—
Ground terminal (for X’tal system)
38
AVSSL
—
Ground terminal (for L-ch side D/A converter section, analog system)
39
L2
O
L-ch PLM signal 2 output terminal
40
AVDDL
—
Power supply terminal (+5V) (for L-ch side D/A converter section, analog system)
41
L1
O
L-ch PLM signal 1 output terminal
42
VDD2
—
Power supply terminal (+5V) (for L-ch side D/A converter section, digital system)
43
VDD1
—
Power supply terminal (+5V) (for A/D converter section, digital system)
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