Sony HCD-XB8 / LBT-XB8AV / MDS-B5 Service Manual ▷ View online
— 81 —
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
Pin No.
Pin Name
I/O
Function
RF M
RFTC
LD
PD
PD1
PD2
FE BIAS
F
E
EI
VEE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
VC
FZC
I
I
O
I
I
I
I
I
I
–
–
O
I
I
I
I
I
O
I
RF summing amplifier inverted input
The RF amplifier gain is determined by the resistance connected between this pin and
RFO pin
External time constant setting pin during RF level control
APC amplifier output
APC amplifier input
RF I-V amplifier inverted input
Connect these pins to the photo diode A+C and B+D pins
Bias adjustment of focus error amplifier
Leave this pin open for automatic adjustment
F I-V and E I-V amplifier inverted input
Connect these pins to photo diodes F and E
I-V amplifier E gain adjustment
(When not using automatic balance adjustment)
Negative power supply
Tracking error amplifier output
E-F signal is output
Comparator input for balance adjustment
(Input from TEO through LPF)
Tracking error input
Window comparator input for ATSC detection
Trackig zero-cross comparator input
Capacitor connection pin for defect time constant
(V
CC
+ V
EE
)/2 direct voltage output
Focus zero-cross comparator input
• Abbreviation
APC
: Auto Power Control
— 82 —
Pin No.
Pin Name
I/O
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
• IC103 DIGITAL SIGNAL PROCESSOR (CXD2519Q)
–
–
O
O
O
O
I
O
O
I
I
I
I
I
O
O
O
I
I
I
I
O
I
–
–
O
O
O
O
I
I
I
O
O
I
O
I
O
O
I
+5V power supply
Ground
Lch “L” detection flog (Not used)
Rch “L” detection flog (Not used)
Test output (Not used)
Master clock divider output (Not used)
Clock input for SQSO read out
Serial output for Sub-Q 80bit
SENS signal output to CPU
Serial data input, supplied from CPU
Latch input, supplied from CPU
Serial data transfer clock input, supplied from CPU
SENS input from IC101
Numbers of track jump counted signal input
Serial data output to IC101
Serial data latch output to IC101
Serial data transfer clock output to IC101
Micro computer demodulation interface (Input A)
Micro computer demodulation interface (Input B)
Micro computer demodulation interface (Input C)
Micro computer demodulation interface (Input D)
Micro computer demodulation interface (Output)
Focus OK input
+5V power supply
Ground
Output to control ON/OFF of spindle motor (Not used)
Output to control spindle motor servo
Output to control spindle motor servo (Not used)
GFS is sampled by 460Hz
Input to control the outside spindle motor
Test pin (Connected to ground)
Test pin (Connected to ground)
Charge-pump output (Not used)
Charge-pump output (Not used)
VCO2 oscillator input (Not used)
VCO2 oscillator output (Not used)
VCO2 control voltage input
Charge-pump output to master PLL
Filter output to master PLL
Filter input for master PLL
VDD
VSS
LMUT
RMUT
ACDT
CKOUT
SQCK
SQSO
SENS
DATA
XLAT
CLOK
SEIN
CNIN
DATO
XLTO
CLKO
SPOA
SPOB
SPOC
SPOD
XLON
FOK
VDD
VSS
MON
MDP
MDS
LOCK
PWMI
TES0
TES1
VPCO2
VPCO1
VCKI
V16M
VCTL
PCO
FILO
FILI
• Abbreviation
GFS
: Guarded Frame Sync
PLL
: Phase Locked Loop
— 83 —
Pin No.
Pin Name
I/O
Function
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
AVSS
CLTV
AVDD
RF
BIAS
ASYI
ASYO
ASYE
WDCK
LRCK
LRCKI
PCMD
PCMDI
BCK
BCKI
VSS
VDD
GTOP
XUGF
XPLCK
GFS
RFCK
C2PO
XRAOF
MNT3
MNT1
MNT0
XTSL
FSTT
C4M
DOUT
EMPH
EMPHI
WFCK
SCOR
SBSO
EXCK
VSS
VDD
SYSM
–
I
–
I
I
I
O
I
O
O
I
O
I
O
I
–
–
O
O
O
O
O
O
O
O
O
O
I
O
O
O
O
I
O
O
O
I
–
–
I
Analog ground
Control voltage input for VCO
Analog power supply
EFM signal input
Asymmetry circuit constant current input
Asymmetry comparate voltage input
EFM full swing output (“L” =V
SS
, “H” =V
DD
)
Asymmetry circuit ON/OFF (“L”=OFF, “H”=ON)
D/A interface Word clock f=2fs (Not used)
D/A interface LR clock output f=Fs
D/A interface LR clock input f=Fs
D/A interface Serial data output
D/A interface Serial data input
D/A interface Bit clock output
D/A interface Bit clock input
Ground
+5V power supply
Not used
Not used
EFM decoder PLL clock output
“H” Playback EFM sync and interpolation protection timming much
Read Frame Clock signal output
Not used
Internal RAM overflow detection signal output (Not used)
Not used
Not used
Not used
Not used
2/3 divider output (Not used)
4.2336MHz output(Not used)
Digital audio signal output
Playback disc output in emphasis mode
“H” =Input when de-emphasis ON
Write Frame Clock signal output
Sub-code sync output
Sub-P through Sub-W serial output
Clock input for SBSO read-out
Ground
+5V power supply
System mute input
• Abbreviation
EFM
: Eight to Fourteen Modulation
— 84 —
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
Function
I/O
—
AVSS
AVDD
AOUT1
AIN1
LOUT1
AVSS
XVDD
XTAI
XTAO
XVSS
AVSS
LOUT2
AIN2
AOUT2
AVDD
AVSS
—
—
XRST
–
–
–
O
I
O
–
–
I
O
–
–
O
I
O
–
–
–
–
I
Not used
Analog ground
Analog power supply
Lch analog output
Lch opamp input
Lch line output
Analog ground
Master clock power supply
X’tal oscillator circuit input
X’tal oscillator circuit output
Master clock ground
Analog ground
Rch line output
Rch opamp input
Rch analog output
Analog power supply
Analog ground
Not used
Not used
Sysyem reset input
Pin Name
Pin No.
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