Sony HCD-VX77J / MHC-VX77 / MHC-VX77J Service Manual ▷ View online
49
• IC502 MPEG DECODER, MECHANISM CONTROL (M30624MCA-A34FP) (VIDEO Board (1/3))
Pin No.
Pin Name
I/O
Function
1
SENSE
I
Internal state (SENSE) monitor input (IC101)
2
SENSE CLK
O
Serial data reading clock output (IC101)
3
RESOLUTION
O
Serial data output (IC101)
4
CROMA LEVEL
O
Lach output (IC101)
5
DSP CLK
O
Serial data clock output (IC101)
6
TSENS
I
Not used
7
REMOTE IN
I
Not used
8
BYTE
I
External bus width change input (Connected to ground)
9
CNVSS
–
Ground
10
DSP MUTE
O
Mute output (IC101) “H” : mute
11
CTRL1 (L : DOUBLE)
O
Double change output (IC101) “L” : double
12
XRESET
I
System reset input “L” : reset
13
XOUT
O
Main clock output (10MHz)
14
VSS
–
Ground
15
XIN
I
Main clock input (10MHz)
16
VCC
–
+5V power supply
17
NMI
I
Requests mask disable interruption input (Connected to +5V)
18
SCOR
I
Subcode sync input (IC101)
19
D SENS
I
Not used
20
CL680 INT
I
Video CD interruption input (IC505)
21
CL680 HSEL
O
Video CD select data of the host MPU (IC505)
22
DF LATCH
O
Digital filter latch output (IC509)
23
CL680 HRDY
I
Ready signal input for communication to the host MPU (IC505)
24
680 RESET
O
Video CD reset output (IC505) “L” : reset
25
H. SYNC IN
I
H. sync signal input
26
BGP
I
BGP output
27
LPH
O
Double control output (IC101) “H” : double
28
LD ON
O
Laser diode ON/OFF output
29
IIC. CLK
I/O
IIC clock input from master control
30
IIC. DATA
I/O
IIC data input from master control
31
DATA1O
O
Serial 1 data output (IC505, 509)
32
DATA1I
I
Serial 1 data input (IC505, 509)
33
CLK1
O
Serial 1 clock output
34
RTS1
O
35
XVLEVEL. DOWN
O
Fix the video signal output level output
36
SUBQ DATA
I
Serial 2 data input for subcode sync reading
37
SUBQ CLK
I
Serial 2 clock input for subcode sync reading
38
P. ON
I
Not used
39
BUS XRDY
I
Not used
40
BUS
I
Not used
41
BUS XHOLD
I
Not used
42, 43
BUS
I
Not used
44
BUS XRD
I
Model selection input “L” : chinese model, “H” : except chinese model
45
V. SYNC
I
V sync signal input
50
I/O
Function
Pin No.
Pin Name
46
BUS XWRL
I
Not used
47
LO. BOOST
I
Not used
48
AUDIO MUTE
O
Audio mute output “L” : mute (Not used)
49
LOAD OUT
I
Not used
50
LOAD IN
I
Not used
51
INSW
I
Not used
52
OUTSW
I
Not used
53
MODEL 1
I
L : System input (Fixed at “L”)
54
MODEL 2
I
L : System input (Fixed at “L”)
55
TBLL
I
Not used
56
TBLR
I
Not used
57
ENC 1
I
Not used
58
ENC 2
I
Not used
59
ENC 3
I
Not used
60
—
I
Not used
61
—
I
Not used
62
VCC
–
+5V power supply
63
—
I
Not used
64
VSS
–
Ground
65
V. MUTE
O
Video mute output “L”
66 to 72
A6 to A0
I
Not used
73
TEST LED
O
TEST LED for MPEG decoder
74
TEST 1
I
Test mode for Video CD check
75
TEST 2
I
Test mode for servo check
76
TEST 3
I
Not used
77
DEVICE RESET
O
Device system rest output “L” : reset
78
STANDBY
I
Not used
79
FL CS
I
Not used
80
FL
I
Not used
81 to 88
D7 to D0
I
Not used
89
MIC CTRL
I
Not used
90
KEY 1
I
Not used
91
KEY 2
I
Not used
92
KEY 3
I
Not used
93
NY/PAL
I
NTSC/PAL select switch input (Not used)
94
MUSIC VOL
I
Not used
95
DSP DATA
O
Serial data output (IC101)
96
AVSS
–
A/D converter ground
97
DSP LATCH
O
Serial data latch output (IC101)
98
VREF
I
A/D converter reference voltage input (Connected to +5V)
99
AVCC
–
A/D converter +5V power supply
100
AMP. ON
I
Not used
51
Function
Pin Name
1
NC
–
Not used
2
VSS
–
Ground
3
CD-BCK
I
CD Decode bit clock
4
CD-DATA
I
CD Decode data
5
CD-LRCK
I
CD Decode Left or Right channel selection clock
6
CD-C2PO
I
CD Decode C2 error data
7
NC
–
Not used
8
NC
–
Not used
9
NC
–
Not used
10
MD0
I/O
Data bus between Microcode ROM/DRAM and CL680
11
MD1
I/O
Data bus between Microcode ROM/DRAM and CL680
12
MD2
I/O
Data bus between Microcode ROM/DRAM and CL680
13
MD3
I/O
Data bus between Microcode ROM/DRAM and CL680
14
MD4
I/O
Data bus between Microcode ROM/DRAM and CL680
15
MD5
I/O
Data bus between Microcode ROM/DRAM and CL680
16
VSS
–
Ground
17
MD6
I/O
Data bus between Microcode ROM/DRAM and CL680
18
VDD3
–
+3.3V Power supply
19
MD7
I/O
Data bus between Microcode ROM/DRAM and CL680
20
VSS
–
Ground
21
MD8
I/O
Data bus between Microcode ROM/DRAM and CL680
22
VDD3
–
+3.3V Power supply
23
MD9
I/O
Data bus between Microcode ROM/DRAM and CL680
24
MD10
I/O
Data bus between Microcode ROM/DRAM and CL680
25
MD11
I/O
Data bus between Microcode ROM/DRAM and CL680
26
MD12
I/O
Data bus between Microcode ROM/DRAM and CL680
27
MD13
I/O
Data bus between Microcode ROM/DRAM and CL680
28
MD14
I/O
Data bus between Microcode ROM/DRAM and CL680
29
MD15
I/O
Data bus between Microcode ROM/DRAM and CL680
30
NC
–
Not used
31
NC
–
Not used
32
NC
–
Not used
33
NC
–
Not used
34
NC
–
Not used
35
NC
–
Not used
36
NC
–
Not used
37
MCE
O
Chip enable signal to Microcode ROM
38
MWE
O
Write enable signal to DRAM
39
VSS
–
Ground
40
CAS
O
Column address strove : Latch the column address to DRAM
41
VDD3
–
+3.3V power supply
42
RAS0
O
Row address strove : Latch row address to DRAM
43
RAS1
–
Not used
44
MA10
O
Address data from CL680 to Microcode ROM
45
MA9
O
Address data from CL680 to Microcode ROM
Pin No.
I/O
• IC505 CD DECODER, SYSTEM CONTROL (CL680T-D1) (VIDEO Board (2/3))
52
46
MA8
O
Address data from CL680 to Microcode ROM/DRAM
47
VSS
–
Ground
48
MA7
O
Address data from CL680 to Microcode ROM/DRAM
49
VDD3
–
+3.3V Power supply
50
MA6
O
Address data from CL680 to Microcode ROM/DRAM
51
MA5
O
Address data from CL680 to Microcode ROM/DRAM
52
MA4
O
Address data from CL680 to Microcode ROM/DRAM
53
VSS
–
Ground
54
MA3
O
Address data from CL680 to Microcode ROM/DRAM
55
VDD3
–
+3.3V Power supply
56
MA2
O
Address data from CL680 to Microcode ROM/DRAM
57
MA1
O
Address data from CL680 to Microcode ROM/DRAM
58
MA0
O
Address data from CL680 to Microcode ROM/DRAM
59
PGIO7
I/O
Not used
60
RESET
I
Reset signal input from the host MPU
61
VDDMAX-IN
I
Fix the maxium input voltage each input pin and I/O pin
62
NC
–
Not used
63
NC
–
Not used
64
NC
–
Not used
65
AGND DAC
–
Ground
66
AVDD DAC
–
+3.3V Power supply
67
COMPOS OUT
O
Not used
68
AGND DAC
–
Ground
69
Y-OUT
O
Luminance signal out
70
AVDD DAC
–
+3.3V Power supply
71
AGND DAC
–
Ground
72
RREF
I
Fix the video signal output level
73
(1.235V) VREF
O
Reference voltage (+1.235V)
74
AVDD DAC
–
+3.3V Power supply
75
C-OUT
O
Chrominance signal out
76
AGND DAC
–
Ground
77
(GCK INT) CLK SEL
I
GCK selection “H”; Internal, “L”; External
78
CLK SEL
I
DA-XCK selection (1)
79
CLK SEL
I
DA-XCK selection (2)
80
VSS
–
Ground
81
RESERVED
I
Selection the operation clock 42.336MHz
82
VDD3
–
+3.3V Power supply
83
DA-EMP
–
Not used
84
RESERVED
–
Not used
85
AGND PLL
–
Ground
86
DA-XCLK
I
Main reference clock input (16.9344MHz=384fs)
87
AVDD PLL
–
+3.3V
88
PGIO4
I/O
Not used
89
PGIO5
I/O
Not used
90
PGIO6
I/O
Not used
Pin No.
Pin Name
I/O
Function
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