Sony HCD-VX555 / HCD-VX555J / MHC-VX555 / MHC-VX555J Service Manual ▷ View online
53
HCD-VX555/VX555J
1
DVDD0
—
Digital power supply
2
XRST
I
System reset
3
MUTE
I
Muting selection pin
4
DATA
I
Serial data input, supplied from CPU
5
XLAT
I
Latch input, supplied from CPU
6
CLOK
I
Serial data transfer clock input, supplied from CPU
7
SENS
O
SENS output
8
SCLK
I
SENS serial data read-out clock
9
ATSK
I/O
Input pin for anti-shock (Ground)
10
WFCK
O
WFCK (Write Frame Clock) output (Not used)
11
XUGF
O
XUGF output (Not used)
12
XPCK
O
XPCK output (Not used)
13
GFS
O
GFS output (Not used)
14
C2P0
O
C2PO output
15
SCOR
O
Sub-code sync output
16
CM4
O
4.2336MHz output (Not used)
17
WDCK
O
48-bit slot D/A interface word clock (Not used)
18
DVSS
—
Digital ground
19
COUT
O
Numbers of track counted signal output (Not used)
20
MIRR
O
Mirror signal output (Not used)
21
DFCT
O
Defect signal output (Not used)
22
FOK
O
Focus OK output (Not used)
23
PWM1
I
(Not used)
24
LOCK
I/O
GFS in sampled by 460Hz (Not used)
25
MDP
O
Output to control spindle motor servo
26
SSTP
I
Input signal to detect disc inner most trak
27
FST0
O
2/3 divider output (Not used)
28
DVDD1
—
Digital power supply
29
SFDR
O
30
SRDR
O
31
TFDR
O
32
TRDR
O
33
FFDR
O
34
FRDR
O
35
DVSS1
—
Digital ground
36
TEST
I
37
TES1
I
38
VC
I
Center voltage input
39
FE
I
FOCUS error signal input
40
SE
I
Sled error signal input
Function
Pin Name
Pin No.
I/O
• IC101 CXD3068Q (DIGITAL SIGNAL PROCESSOR) (BD Board)
Sled drive output
Tracking drive output
Focus drive output
TEST pin connected normally ground
54
HCD-VX555/VX555J
Pin Name
I/O
41
TE
I
Tracking error signal input
42
CE
I
Center servo analog input
43
RFDC
I
RF signal input
44
ADI0
O
Test pin (Not used)
45
AVSS0
—
Analog ground
46
IGEN
I
Power supply pin operational amplifiers
47
AVDD
—
Analog power supply
48
ASYO
O
EFM full swing output
49
ASYI
I
Asymmetry comparate voltage input
50
RFAC
I
EFM signal input
51
AVSS1
—
Analog ground
52
CLTV
I
Control voltage input for master VCO
53
FILO
O
Filter output for master PLL
54
FILI
I
Filter input for master PLL
55
PCO
O
Charge-pump output for master PLL
56
AVDD1
—
Analog power supply
57
BIAS
I
Asymmetry circuit constant current input
58
VCTL
I
Control voltage input for variable pitch PLL
59
V16M
I/O
16.9344MHz output (Not used)
60
VPCO
O
Charge-pump output for variable pitch PLL (Not used)
61
DVDD2
—
Digital power supply
62
ASYE
I
Asymmetry circuit ON/OFF (Connected to +5V.)
63
MD2
I
Digital-out ON/OFF control (Connected to +5V.)
64
DOUT
O
Digital-out output
65
LRCK
O
48-bit slot D/A interface, LR clock output
66
PCMD
O
48-bit slot D/A interface, Serial deta output
67
BCLK
O
48-bit slot D/A interface, bit clock output
68
EMPH
O
Playback disc output in emphasis mode (Not used)
69
XTSL
I
X’tal selection input pin
70
DVSS2
—
Digital ground
71
XTAI
I
X’tal oscillator circuit input
72
XTAO
O
X’tal oscillator circuit output (Not used)
73
SOUT
O
74
SOCK
O
(Not used)
75
XOCT
O
76
SQSO
O
Sub-Q serial output
77
SQCK
I
Clock input for SQSO read-out
78
SCSY
I
Sub-code input
79
SBSO
O
Sub-P through Sub-W serial output (Not used)
80
EXCR
I
Clock input for SBSO read-out
Pin No.
Function
55
HCD-VX555/VX555J
• IC601 MB90M407PF-G-103-BND (DISPLAY CONTROL) (PANEL BOARD)
Pin No.
1 - 5
6 - 10
11
12 - 22
23
24 - 42
43
44 - 47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64 - 66
67 - 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85 - 91
92
93 - 100
I/O
O
O
—
O
—
O
—
O
—
I
I
I
O
O
O
O
O
O
O
O
O
O
—
—
I
I
I
I
I
O
O
O
—
I
I
I
—
—
—
—
—
O
O
Pin Name
G5-1
P1-5
VSS-IO
P6-16
VDD-FIP
P17-35
VSS-IO
P36-39
VKK
MD0
MD1/VDD-VFT
MD2
REC/PAUSE LED
ENTER LED
TAPE A/B LED
TUNER LED
MD/VIDEO LED
CD/VCD LED
GAME IN LED
DISC 1 LED
IIC DATA
IIC CLK
AVCC
AVSS
KEY0-2
BPF4-1
BPF0
BPF5
ALL BAND
DISC 2 LED
DISC 3 LED
VIDEO SWITCH
RESET
HEADPHONE
VOL 1B
VOL 1A
VSS-CPU
X0
X1
VCC-CPU
N.C.
SOFT TEST
G13-6
Description
FL grid signal output
FL segment signal output
Ground for I/O port
FL segment signal output
Power supply for FL tube
FL segment signal output
Ground for I/O port
FL segment signal output
-30V for FL tube
Micom operation mode (10k pull-up)
Micom operation mode
Micom operation mode (10k pull-down)
REC/PAUSE LED control signal output
ENTER LED control signal output
TAPE A/B LED control signal output
TUNER LED control signal output
MD/VIDEO LED control signal output
CD/VCD LED control signal output
GAME IN LED control signal output
DISC 1 LED control signal output
IIC DATA signal output
IIC CLK signal output
Power supply for A/D
Ground for A/D
Key input (A/D)
BPF input (A/D)
SUPER LOW FREQUENCY (BPF input)
BPF input (A/D)
L+R (BPF input)
DISC 2 LED control signal output
DISC 3 LED control signal output
Not used
Reset signal input
Headphone detect signal input (H=ON,L=OFF)
Volume 1B signal input
Volume 1A signal input
Ground for CPU
Oscillator
Oscillator
Power supply for CPU
Not used
Not used
FL grid signal output
56
HCD-VX555/VX555J
• IC502 M30622MGA-A45FP (CD MECHANISM CONTROLLER) (VIDEO BOARD)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42, 43
44
45
46
47
48
49
50
51
I/O
I
O
O
O
O
—
—
I
—
O
O
I
O
—
I
—
I
I
—
I
I
O
—
O
—
O
—
O
I/O
I/O
O
I
O
O
O
I
I
—
I
—
I
—
I
I
O
—
—
—
—
—
Description
Internal status (SENSE) signal input from the CXD3068Q (IC101)
Sense serial data reading clock signal output to the CXD3068Q (IC101)
Y resolution output
Chroma level output
Serial data transfer clock signal output to the CXD3068Q (IC101)
Not used (open)
Not used (open)
External data bus line byte selection signal input “L”: 16 bit, “H”: 8 bit (fixed at “L”)
Ground terminal
Muting on/off control signal output to the CXD3068Q (IC101) “H”: muting on
Clock selection signal output to the CXD3068Q (IC101) “L”: 16.9344 MHz (double speed), “H”: 33.8688 MHz
Reset signal input from the system controller (IC501) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
Main system clock output terminal (10 MHz)
Ground terminal
Main system clock input terminal (10 MHz)
Power supply terminal (+5V)
Non-maskable interrupt input terminal (fixed at “H” in this set)
Subcode sync (S0+S1) detection signal input from the CXD3068Q (IC101)
Not used (open)
Interrupt request signal input from the CL680 (IC505)
Horizontal sync signal input
Burst gate pulse signal output
Not used (open)
PWM3 signal output to the CXA2581N (IC103)
Not used (open)
PWM2 signal output to the CXA2581N (IC103)
Not used (open)
PWM1 signal output to the CXA2581N (IC103)
I
2
C clock signal
I
2
C data signal
Serial data output to the FLASH writer
Serial data input from the FLASH writer
Serial data transfer clock signal output to the FLASH writer
RTS signal to the FLASH writer
Serial data0 output to the CL680 (IC505)
Serial data0 input from the CL680 (IC505)
Data reading clock signal input from the CL680 (IC505)
Not used (open)
Ready signal input terminal Not used (fixed at “H”)
Not used (open)
Hold signal input terminal from the FLASH writer
Not used (open)
OSD language select input terminal “H”: English, “L”: China
Vertical sync signal input
Bus write signal output to the FLASH writer
Not used (open)
Not used (open)
Not used (open)
Not used (open)
Not used (fixed at “H”)
Pin Name
SENSE
SENSE CLK
RESOLUTION
CHROMA LEVEL
DSP CLK
TSENS
REMOTE IN
BYTE
CN VSS
DSP MUTE
CTRL1
XRESET
XOUT
VSS
XIN
VCC
NMI
SCOR
DSENS
CL680INTERRUPT
H.SYNC IN
BGP
PWM3(BD)
PWM2(BD)
PWM1(BD)
12C.CLK
12C.DATA
DATA1O
DATA1I
CLK1
RTS1
DATAO
DATAI
CLK1
P.ON
BUS XRDY
BUS
BUS XHOLD
BUS
OSD.LANGUAGE
VSYNC
BUS XWRL
LO.BOOST
AUDIO MUTE
LOAD OUT
LOAD IN
INSW
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