Sony HCD-VX550 / MHC-VX550 Service Manual ▷ View online
53
Pin No.
Pin Name
I/O
Description
42, 43
BUS
O
Not used (open)
44
BUS XRD
O
O
Bus read signal output.
45
BUS
Not used.
46
BUS XWR
O
Bus write signal output.
47
8830-CS
O
Chip select signal output. (IC505)
48
AUDIO MUTE
O
Audio muting on/off control signal output terminal “L”: muting on Not used (open)
49
LOAD OUT
O
Loading motor drive signal output terminal Not used (open)
50
LOAD IN
O
Loading motor drive signal output terminal Not used (open)
51
INSW
I
Disc detection (load in) switch input terminal Not used (fixed at “H”)
52
OUTSW
I
Disc detection (load out) switch input terminal Not used (fixed at “H”)
53
MODEL1
I
Destination setting terminal (fixed at “L”)
54
MODEL2
I
Destination setting terminal (fixed at “L”)
55 to 61
A15 to A9
Address signal output for the external device. Not used
O
62
VCC
—
Power supply terminal (+5V)
63
A8
O
Address signal output for the external device. Not used (open)
64
VSS
—
Ground terminal
65 to 72
A7 to A0
O
Address signal output for the external device.
73
TEST LED
O
LED drive signal output for the self diagnosis indicator (D502) Normally: “L” (LED on)
74
TEST1
I
Setting terminal for the test mode 1 (for VCD check)
Normally: fixed at “H” (“L”: test mode)
Normally: fixed at “H” (“L”: test mode)
75
TEST2
I
Setting terminal for the test mode 2 (for SERVO check)
Normally: fixed at “H” (“L”: test mode)
Normally: fixed at “H” (“L”: test mode)
76
TEST3
I
Setting terminal for the test mode 3 Normally: fixed at “H” (“L”: test mode)
Not used (fixed at “H”)
Not used (fixed at “H”)
77
DEVICE RESET
O
System reset signal output to the CXD3008Q (IC101), BA5974FP (IC102) and D/A converter
(IC509) “L”: reset
(IC509) “L”: reset
78
STANDBY
O
Standby on/off control signal output terminal Not used (open)
79
FL CS
O
Chip select signal output terminal Not used (open)
80
FLBLK
O
Blank control signal output terminal Not used (open)
81 to 88
D7 to D0
I/O
Two-way data bus with the external device Not used (open)
89
NC
NC
Not used.
Not used.
90 to 92
KEY1 to KEY3
I
Key input terminal Not used (fixed at “H”)
93
NT/PAL
I
Video system select switch (S501) input terminal
“L”: PAL, “H”: NTSC, Center voltage: AUTO
“L”: PAL, “H”: NTSC, Center voltage: AUTO
94, 95
NC
Not used.
96
AVSS
—
—
—
NC
Not used.
—
—
Ground terminal (for A/D conversion)
97
98
VREF
I
Reference voltage (+5V) input terminal (for A/D conversion)
99
AVCC
—
Power supply terminal (+5V) (for A/D conversion)
100
54
Pin No.
1
2 to 4
5
6
7
8 to 11
12
13
14
15
16
17
19
27
29
36
38
40
42
47
49
52
53,54
55
56
57
58 to 60
61
62
63
64
65
66
67
68
69
70
71
72 to 74
75
I/O
I/O
I/O
-
I/O
-
I/O
-
I
-
O
O
-
-
-
-
-
-
-
-
-
-
I/O
I/O
-
I/O
-
I/O
-
I/O
-
I/O
-
I/O
-
I/O
-
I/O
-
I/O
-
Description
Programmable I/O pins.
8bit bl-directional host data bus. Host writes data to the decoder Code FIFO via HDATA[7:0]. MSB of the 32-bit
word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via
HDATA[7:0].
3.3-V supply voltage for core logic and I/O signals.
8bit bl-directional host data bus. Host writes data to the decoder Code FIFO via HDATA[7:0]. MSB of the 32-bit
word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via
HDATA[7:0].
Ground for core logic and I/O signals.
8bit bl-directional host data bus. Host writes data to the decoder Code FIFO via HDATA[7:0]. MSB of the 32-bit
word is written first. The host also reads and writes the decoder internal registers and local SDRAM/ROM via
HDATA[7:0].
3.3-V supply voltage for core logic and I/O signals.
Hardware reset. An external device asserts RESET (active LOW) to execute a decoder hardware reset. To ensure
proper initialization after power in stable, assert RESET for at least 20Ms.
Ground for core logic and I/O signals.
Active LOW to indicate host initiated transfer is not complete. WAIT is asserted after the falling edge of CS and
reasserted when decoder is ready to complete transfer cycle. Open drain signal, must be pulled-up to 3.3 volts.
Driven high for 10 ns before tristate.
Host interrupt. Open drain signal, must be pulled-up to 3.3 volts. Driven high for 10 ns before tristate.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
Programmable I/O pins.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Pin Name
PIO[10:0]
HDATA[7:0]
VDD
HDATA[7:0]
VSS
HDATA[7:0]
VDD
RESET
VSS
WAIT
INT
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
PIO[10:0]
MDATA[15:0]
VDD
MDATA[15:0]
VSS
MDATA[15:0]
VDD
MDATA[15:0]
VSS
MDATA[15:0]
VDD
MDATA[15:0]
VSS
MDATA[15:0]
VDD
MDATA[15:0]
VSS
MDATA[15:0]
VDD
VIDEO BOARD IC506 CL8830-PDQ (MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR)
55
Pin No.
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98 to 100
101
102
103
104 to 106
107
108
109
110 to 112
113
114
115
116
117
118
119
120 to 122
123
124
125
126,127
128
129
133
134
136
138
I/O
I/O
-
I/O
O
O
-
O
-
O
O
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
-
O
O
I/O
I/O
-
-
I/O
Description
Memory address.
Ground for core logic and I/O signals.
Memory address.
SDRAM LDQM.
SDRAM UDQM.
3.3-V supply voltage for core logic and I/O signals.
SDRAM/EDO write enable. Decoder asserts active LOW to request a write operation to the SDRAM array.
Ground for core logic and I/O signals.
SDRAM system cclock.
Active LOW SDRAM column address.
Active LOW SDRAM row address.
3.3-V supply voltage for core logic and I/O signals.
Active LOW SDRAM bank select.
Ground for core logic and I/O signals.
Active LOW SDRAM bank select.
3.3-V supply voltage for core logic and I/O signals.
Active LOW EDO DRAM column address strobe.
Ground for core logic and I/O signals.
Active LOW EDO DRAM Row address strobe.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
3.3-V supply voltage for core logic and I/O signals.
Memory address.
Ground for core logic and I/O signals.
Memory address.
ROM chip select. Open drain signal, must be pulled-up to 3.3 volts.
Programmable I/O pins.
Programmable I/O pins.
3.3-V supply voltage for core logic and I/O signals.
Ground for core logic and I/O signals.
Programmable I/O pins.
Pin Name
MDATA[15:0]
VSS
MDATA[15:0]
LDQM
UDQM
VDD
MWE
VSS
SD-CLK
SD-CAS
SD-RAS
VDD
SD-CS[1:0]
VSS
SD-CS[1:0]
VDD
EDO-CAS
VSS
EDO-RAS
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
VSS
MADDR[20:0]
VDD
MADDR[20:0]
VSS
MADDR[20:0]
ROM-CS
PIO[10:0]
PIO[10:0]
VDD
VSS
PIO[10:0]
56
Pin No.
141
142,143
144
145
146
147
148
149
150
151
152
153
154,155
157
158
160
161
162
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
190
I/O
I/O
O
-
O
-
I/O
O
-
O
-
O
I/O
O
I/O
I/O
-
O
-
O
O
-
I/O
-
I
I
I
I/O
-
-
I
I
-
I
-
I
-
I
I
I/O
Description
Programmable I/O pins.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
3.3-V supply voltage for core logic and I/O signals.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Ground for core logic and I/O signals.
Programmable I/O pins.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
3.3-V supply voltage for core logic and I/O signals.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Ground for core logic and I/O signals.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Programmable I/O pins.
Video data bus. Byte serial CdYCrY data synchronous with VCLK. At power-up, the decoder does not drive
VDATA. During boot-up, the decoder uses configuration parameters to drive or 3-state VDATA.
Horizontal sync. The decoder begins outputting pixel data for a new horizontal line after the falling (active) edge
of HSYNC.
Vertical sync. Bi-directional, the decoder outputs the top border of a new field on the first HSYNC after the
falling edge of VSYNC. VSYNC can accept vertical synchronization or top/bottom field notification from an
external source. (VSYNC HIGH=bottom field. VSYNC LOW=Top field)
3.3-V supply voltage for core logic and I/O signals.
Serial audio samples relative to DA-BCK clock.
Ground for core logic and I/O signals.
PCM left-right colck. Identifies the channel for each audio sample. the polarity is programmable.
PCM bit clock. Divided by 8 form DA-XCX, DA-BCK can be either 48 or 32 times the sampling clock.
3.3-V supply voltage for core logic and I/O signals.
Audio external frequency clock. Used to generate DA-BCK and DA-LRCK. DA-XCK can be either 384 or 256
times the sampling frequency.
Ground for core logic and I/O signals.
PCM input data, two channels. Serial audio samples relative to DA-BCK clock, resulting in downmixed audio output.
PCM input left-right clock.
PCM input bit clock.
Programmable I/O pins.
3.3-V supply voltage for core logic and I/O signals.
3.3-V analog supply voltage.
Video clock. Clocks out data on input. VDATA[7:0]. Clock is typically 27 MHz.
System clock. Decoder requires an external 27MHz TTL oscillator. Drive with the same 27-MHz as VCK.
Analog ground for PLL.
Serial CD data.
3.3-V supply voltage for core logic and I/O signals.
Programmable polarity 16-bit word synchronization to the decoder (right channel HIGH).
Ground for core logic and I/O signals.
CD bit clock. Decoder accept multiple BCK rates.
Asserted HIGH indicates a corrupted byte. Decoder keeps the previous valid picture on-screen until the next valid
picture is decoded.
Programmable I/O pins.
Pin Name
PIO[10:0]
VDATA[7:0]
VDD
VDATA[7:0]
VSS
PIO[10:0]
VDATA[7:0]
VDD
VDATA[7:0]
VSS
VDATA[7:0]
PIO[10:0]
VDATA[7:0]
HSYNC
VSYNC
VDD
DA-DATA
VSS
DA-LRCK
DA-BCK
VDD
DA-XCX
VSS
DAI-DATA
DAI-LRCK
DAI-BCK
PIO[10:0]
VDD
A-VDD
VCLK
SYSCLK
A-VSS
CD-DATA
VDD
CD-LRCK
VSS
CD-BCK
CD-C2PO
PIO[10:0]
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