Sony HCD-VP800AV / MHC-VP800AV Service Manual ▷ View online
57
HCD-VP800AV
58
MOD0
I
Operation mode signal input (L : single chip mode, H : use prohibited)
59
EXLOCK
I
Lock signal input
60
VDDI
I
Power supply
61
VSS
—
Ground
62, 63
A17, A16
O
Not used (open)
64 - 66
A15 - A13
O
External memory address output (SRAM)
67
GP10
O
LRCK0
68
GP9 (DECODE)
O
DECODE
69
GP8 (AUDIO)
I
AUDIO
70
VDDI
I
Power supply
71
VSS
—
Ground
72 - 75
D15 - D12
I/O
External memory data input /output (general port)
76
VDDE
I
Power supply
77 - 80
D11 - D8
I/O
External memory data input /output (general port)
81
VSS
—
Ground
82 - 85
A9 - A12
O
External memory address output (SRAM)
86
TDO
O
Simple emulation data output
87
TMS
I
Simple emulation data input start, end terminal
88
XTRST
I
Simple emulation async BREAK signal input terminal
89
TCK
I
Simple emulation clock signal input
90
TDI
I
Simple emulation data input
91
VSS
—
Ground
92 - 97
A8 - A3
O
External memory address output (SRAM)
98 - 99
D7, D6
I/O
External memory data input/output (SRAM)
100
VDDI
I
Power supply
101
VSS
—
Ground
102 - 105
D5 - D2
I/O
External memory data input/output (SRAM)
106
VDDE
I
Power supply
107 - 108
D1, D0
I/O
External memory data input/output (SRAM)
109 - 110
A2, A1
O
External memory address output (SRAM)
111
VSS
—
Ground
112
A0
O
External memory address output (SRAM)
113
PM
I
PLL initialization input terminal
114 - 115
SDI3, SDI4
I
Not used (connected to ground)
116
SYNC
I
Sync/async selection input (L : sync, H : async)
117 - 119
VSS
—
Ground
120
VDDI
I
Power supply
Pin Name
Pin No.
I/O
Discription
58
HCD-VP800AV
• IC502 M30622MGA-A59FP (CD MECHANISM CONTROLLER) (VIDEO BOARD)
Pin No.
Pin Name
I/O
1
SENSE
I
Internal state (SENSE) monitor input
2
SENSE CLK
O
Serial data reading clock output
3
RESOLUTION
O
Y resolution output
4
CROMA LEVEL
O
Chroma level controll signal output
5
DSP CLK
O
Serial data clock output
6
TSENS
I
Not used (open)
7
REMOTE IN
I
Not used (open)
8
BYTE
I
Not used (Connected to ground)
9
CNVSS
–
Ground
10
DSP MUTE
O
Muting on/off control signal output “H” : muting on
11
CTRL1 (L : DOUBLE)
O
Clock selection signal output (IC101) “L” : double speed (16.9344MHz)
12
XRESET
I
System reset input “L” : reset
13
XOUT
O
Main clock output terminal (10MHz)
14
VSS
–
Ground
15
XIN
I
Main clock input terminal (10MHz)
16
VCC
I
Power supply (+5V )
17
NMI
I
Not used (Connected to +5V)
18
SCOR
I
Subcode sync input
19
D SENS
I
Not used (open)
20
CL680 INT
I
Video CD interruption input
21
H. SYNC IN
I
H. sync signal input
22
BGP
O
Burst gate pulse signal output
23
—
I
Not used (open)
24
PWM3 (BD)
O
PWM3 signal output
25
—
I
Not used (open)
26
PWM2 (BD)
O
PWM2 signal output
27
—
I
Not used (open)
28
PWM1 (BD)
O
PWM1 signal output
29
I2C. CLK
I
IIC clock input from master control
30
I2C. DATA
I
IIC data input from master control
31
DATA1O
O
Serial data output to the FLASH writer
32
DATA1I
I
Serial data input from the FLASH writer
33
CLK1
O
Serial data transfer signal output the FLASH writer
34
RTS1
O
RTS (BUSY) signal to the FLASH writer
35
DATAO
O
Serial data output to MPEG decoder
36
DATA1
I
Serial data input from MPEG decoder
37
CLK1
O
Serial clock output to MPEG decoder
38
P. ON
I
Not used (open)
39
BUS XRDY
I
Not used (connected to +5V)
40
BUS
I
Not used (open)
41
BUS XHOLD
I
Hold signal input terminal from the FLASH writer
42, 43
BUS
I
Not used (open)
44
BUS XRD
I
Not used
45
V. SYNC
I
V sync signal input
46
BUS XWRL
O
Bus write signal output to the FLASH writer
47
LO. BOOST
I
Not used (open)
48
AUDIO MUTE
O
Not used (open)
49
LOAD OUT
I
Not used (open)
50
LOAD IN
I
Not used (open)
Discription
59
HCD-VP800AV
I/O
Pin No.
Pin Name
51
INSW
I
Not used (connected to +5V)
52
OUTSW
I
Not used (open)
53
MODEL 1
I
Not used (open)
54
MODEL 2
I
Not used (open)
55
TBLL
I
Not used (open)
56
TBLR
I
Not used (open)
57
ENC 1
I
Not used (open)
58
ENC 2
I
Not used (open)
59
ENC 3
I
Not used (open)
60
—
I
Not used (open)
61
—
I
Not used (open)
62
VCC
I
Power supply (+5V )
63
—
I
Not used (open)
64
VSS
–
Ground
65
V. MUTE
O
Video mute signal output
66
DAC RESET
O
Audio DAC reset signal output
67 - 72
A5 to A0
I
Not used (open)
73
TEST LED
O
TEST LED terminal
74
TEST 1
I
Test mode terminal
75
TEST 2
I
Test mode terminal
76
TEST 3
I
Test mode terminal
77
DEVICE RESET
O
Device system rest output
78
STANDBY
I
Not used (open)
79
FL CS
I
Not used (open)
80
FL
I
Not used (open)
81
LPH
O
Not used (open)
82
LD ON
O
Laser diode ON/OFF signal output
83
SUBQ CLK
O
Sub-code Q data reading clock signal output
84
SUBQ DATA
I
Sub-code Q data input
85
CL680 HRDY
I
HRDY serial signal input
86
680 RESET
O
Reset signal output to the CL680 (IC505)
87
CL680 HSEL
O
Video CD select data of the host MPU (IC505)
88
DF LATCH
O
Digital filter latch output (IC509)
89
MIC CTRL
I
Not used (open)
90
KEY 1
I
Not used (open)
91
KEY 2
I
Not used (open)
92
KEY 3
I
Not used (open)
93
NY/PAL
I
Not used (open)
94
MUSIC VOL
I
Not used (open)
95
DSP DATA
O
Serial data output
96
AVSS
–
Ground terminal (for A/D conversion)
97
DSP LATCH
O
Serial data latch output
98
VREF
I
A/D converter reference voltage input (Connected to +5V)
99
AVCC
I
A/D converter +5V power supply (+5V) (for A/D conversion)
100
AMP. ON
I
Not used (open)
Discription
60
HCD-VP800AV
6-32.
IC BLOCK DIAGRAMS
IC103
CXA2581N-T4 (BD BOARD)
27
29
30
4
3
EQ IN
9
D
10
F
E
8
C
7
B
6
A
AC SUM
DC_ OFST
RFDCI
28 RFDCO
VC
24 BST
25 VFC
CEI
EQ
APC
5
GND
AC
SUM
26 RFC
AC
VCA
23 RFG
22 VCC
20
21
CE
19 TE_BAL
18 TE
17 FEI
16 FE
1
LD
2
PD
11
SW 12
13
DVCC
14
DVC
15
RFAC
VC
EQ
ON/OFF
VC
VC
VC
VC
DVC
DVC
APC-OFF(Hi-Z)
RW/ROM
(H/L)
DVC
DVC
AVC
DVCC
VC
DVC
RW/ROM
RW/ROM
RW/ROM
RW/ROM
RW/ROM
RW/ROM
DVCC
VCC
VCC
VCC
VOFST
VOFST
VOFST
B
C
A
D
gm
gm
DVCC
IC302
µPC1330HA (MAIN BOARD (1/3))
1
2
3
4
5
6
7
8
9
INVERTER
COMPARATER
SW R1
GND
SW P1
CONT
GND
VCC
SW P2
GND
SW R2
IC11
LA1845 (MAIN BOARD (3/3))
ALC
AGC
REG
GND
VCC
AM
DET
STEREO
SW
P-DET
φ
VCO
304KHz
DECODER
ANTI-BRIDIE
PILOT
CANCEL
FF
38k
FF
19K
∠
PILOT
DET
AM
IF
AM
OSC
AM
MIX
AM/FM
AM
RF.AMP
COMP
BUFF
S-CURVE
IF
BUFF
LEVEL
DET
FM
IF
FM
DET
FM-IN
AM
MIX-OUT
REG
AM
IF-IN
GND
TUNED
STEREO
FM-DET
VCC
IF-REQ
MUTE
AM/FM
VCO
STOP
OSC
FM.SD
AM-AGC
S-METER
AFC
AM-RF
IN
DECODER
OUT
AM
DET-OUT
AM-OSC
DECODER
IN
PLL-IN
PILOT
CANCEL
R-OUT
L-OUT
π
2
FF
19K
∠0
TUNING
DRIVE
24
23
22
21
20
19
13
14
15
16
17
18
1
2
3
4
5
6
12
11
10
9
8
7
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