Sony HCD-VP700 Service Manual ▷ View online
58
HCD-VP700
1
FIPLED16
O
Grid drive signal output to the fluorescent indicator
2 - 5
FIP17 - 20
O
Grid drive signal output to the fluorescent indicator
6 - 10
A1 - A5
O
Segment drive signal output the flourescent indicator tube
11
Vss IO
—
Ground
12 - 22
A6 - A16
O
Segment drive signal output the flourescent indicator tube
23
Vdd FIP
I
Power supply terminal (B+ VFT)
24 - 41
A17 - A34
O
Segment drive signal output the flourescent indicator tube
42
Vss IO
—
Ground
43 - 47
A35 - A39
O
Segment drive signal output the flourescent indicator tube
48
Vkk
I
Power supply terminal (B- for VFT)
49
MD0
I
Chip Mode Select 0
50
MD1 Vdd-VFT
I
Chip Mode Select 1
51
MD2
I
Chip Mode Select 2
52
LED15
O
LED switch signal output
53
LED14
O
LED switch signal output
54
LED13
O
LED switch signal output
55
LED12
O
Not used (open)
56
VOL A
I
Jog dial pulse input from the rotary encoder(A phase input)
57
VOL B
I
Jog dial pulse input from the rotary encoder(B phase input)
58
HEADPHONE
I
HEAD PHONE check (“H” head phone)
59
MULTI CHANNEL LED
O
LED switch signal output
60
I2C DATE
O
IIC data bus SDA signal
61
I2C CLK
O
IIC data bus reading clock (SCL signal)
62
Avcc
I
Power supply terminal (analog)
63
Avss
—
Ground (analog)
64 - 66
KEY0 - KEY2
I
KEY in terminal (A/D input)
67
LED10
O
LED switch signal
68
YL
I/O
Tuoch pad control signal input/output
69
XL
I/O
Tuoch pad control signal input/output
70
XH
I/O
Tuoch pad control signal input/output
71
YH
I/O
Tuoch pad control signal input/output
72
AHH
I
Tuoch pad signal input(A/D input)
73
AHL
I
Tuoch pad signal input(A/D input)
74
AVH
I
Tuoch pad signal input(A/D input)
75
AVL
I
Tuoch pad signal input(A/D input)
76
LED9
O
LED switch signal output
77
RSTX
I
System reset signal input
78
LED8
O
LED switch signal output
79
LED7
O
LED switch signal output
80
LED6
O
LED switch signal output
81
Vss CPU
—
Ground
82
XO
O
Clock output (4MHz)
83
XI
I
Clock input (4MHz)
84
Vcc - CPU
I
Power supply terminal
85
LED5
O
LED switch signal output
86
LED4
O
LED switch signal output
87
LED3
O
LED switch signal output
88
LED2
O
LED switch signal output
89
LED1
O
LED switch signal output
90 - 100
FIP LED5 - 15
O
Grid drive signal output to the fluorescent indicator
Pin Name
Pin No.
I/O
• IC1101 DISPLAY CONTROL (MB90M407APF-G-105-BND) (PANEL Board (1/2))
Discription
59
HCD-VP700
1
VSS
—
Ground
2
XRST
I
Reset signal input
3
EXTIN
I
Not used (connected to ground)
4
FS2
I
Not used (connected to ground)
5
VDDI
I
Power supply
6
FS1
I
Not used (connected to ground)
7
PLOCK
O
Internal PLL lock signal output (Not used)
8
VSS
—
Ground
9
MCLK1
I
Clock signal input (135 MHz)
10
VDDI
I
Power supply
11
VSS
—
Ground
12
MCLK2
O
Not used (open)
13
M/S
I
Switching of master/slave operation 0 : internal clock, 1 : EXTIN clock is used
14
SCKOUT
O
Internal system clock signal output
15
LRCKI1
I
Not used (open)
16
VDDE
I
Power supply
17
BCKI1
I
Not used (open)
18
SDI1
I
Audio IF data input
19
LRCKO
O
Sampling clock output for audio IF serial data
20
BCKO
O
Bit clock output terminal for audio IF serial data
21
VSS
—
Ground
22
KFSIO
I/O
Audio clock signal (364fs/256fs) input/output
23 - 26
SDO1 - SDO4
O
Audio IF serial data output
27
SPDIF
O
Not used (open)
28
LRCKI2
I
Sampling clock input for audio IF serial data
29
BCKI2
I
Bit clock input terminal for audio IF serial data
30
SDI2
I
Audio IF data input
31
VSS
—
Ground
32
HACN
O
Acknowledge signal output for host IF
33
HDIN
I
Serial data input for host IF
34
HCLK
I
Clock input for host IF
35
HDOUT
O
Serial data output for host IF
36
HCS
I
Chip select input for host IF
37
SDCLK
O
Not used (open)
38
CLKEN
O
Not used (open)
39
RAS
O
Not used (open)
40
VDDI
I
Power supply
41
VSS
—
Ground
42
CAS
O
Not used (open)
43
DQM/OE0
O
Not used (open)
44
CS0
O
External memory chip select (SRAM)
45
WE0
O
SRAM write enable output
46
VDDE
I
Power supply
47
WMD1
I
Not used (connected to “H”)
48
VSS
—
Ground
49
WIMD0
I
Not used (connected to ground)
50
PAGE2
O
Not used (open)
51
VSS
—
Ground
52
PAGE1
O
External memory page switching signal output (Not used)
53
PAGE0
O
External memory page switching signal output (Not used)
54
BOOT
I
Not used (connected to ground)
55
BTACT
O
Not used (open)
56
BST
I
Boot stop signal input
57
MOD1
I
Operation mode signal input (L : 386fs, H : 256fs)
• IC601 DECODER (CXD9617R) (DSP Board (1/2))
Pin Name
Pin No.
I/O
Discription
60
HCD-VP700
58
MOD0
I
Operation mode signal input (L : single chip mode, H : use prohibited)
59
EXLOCK
I
Lock signal input
60
VDDI
I
Power supply
61
VSS
—
Ground
62, 63
A17, A16
O
Not used (open)
64 - 66
A15 - A13
O
External memory address output (SRAM)
67
GP10
O
LRCK0
68
GP9 (DECODE)
O
DECODE
69
GP8 (AUDIO)
I
AUDIO
70
VDDI
I
Power supply
71
VSS
—
Ground
72 - 75
D15 - D12
I/O
External memory data input /output (general port)
76
VDDE
I
Power supply
77 - 80
D11 - D8
I/O
External memory data input /output (general port)
81
VSS
—
Ground
82 - 85
A9 - A12
O
External memory address output (SRAM)
86
TDO
O
Simple emulation data output
87
TMS
I
Simple emulation data input start, end terminal
88
XTRST
I
Simple emulation async BREAK signal input terminal
89
TCK
I
Simple emulation clock signal input
90
TDI
I
Simple emulation data input
91
VSS
—
Ground
92 - 97
A8 - A3
O
External memory address output (SRAM)
98 - 99
D7, D6
I/O
External memory data input/output (SRAM)
100
VDDI
I
Power supply
101
VSS
—
Ground
102 - 105
D5 - D2
I/O
External memory data input/output (SRAM)
106
VDDE
I
Power supply
107 - 108
D1, D0
I/O
External memory data input/output (SRAM)
109 - 110
A2, A1
O
External memory address output (SRAM)
111
VSS
—
Ground
112
A0
O
External memory address output (SRAM)
113
PM
I
PLL initialization input terminal
114 - 115
SDI3, SDI4
I
Not used (connected to ground)
116
SYNC
I
Sync/async selection input (L : sync, H : async)
117 - 119
VSS
—
Ground
120
VDDI
I
Power supply
Pin Name
Pin No.
I/O
Discription
61
HCD-VP700
• IC502 M30622MGA-A59FP (CD MECHANISM CONTROLLER) (VIDEO BOARD)
Pin No.
Pin Name
I/O
1
SENSE
I
Internal state (SENSE) monitor input
2
SENSE CLK
O
Serial data reading clock output
3
RESOLUTION
O
Y resolution output
4
CROMA LEVEL
O
Chroma level controll signal output
5
DSP CLK
O
Serial data clock output
6
TSENS
I
Not used (open)
7
REMOTE IN
I
Not used (open)
8
BYTE
I
Not used (Connected to ground)
9
CNVSS
–
Ground
10
DSP MUTE
O
Muting on/off control signal output “H” : muting on
11
CTRL1 (L : DOUBLE)
O
Clock selection signal output (IC101) “L” : double speed (16.9344MHz)
12
XRESET
I
System reset input “L” : reset
13
XOUT
O
Main clock output terminal (10MHz)
14
VSS
–
Ground
15
XIN
I
Main clock input terminal (10MHz)
16
VCC
I
Power supply (+5V )
17
NMI
I
Not used (Connected to +5V)
18
SCOR
I
Subcode sync input
19
D SENS
I
Not used (open)
20
CL680 INT
I
Video CD interruption input
21
H. SYNC IN
I
H. sync signal input
22
BGP
O
Burst gate pulse signal output
23
—
I
Not used (open)
24
PWM3 (BD)
O
PWM3 signal output
25
—
I
Not used (open)
26
PWM2 (BD)
O
PWM2 signal output
27
—
I
Not used (open)
28
PWM1 (BD)
O
PWM1 signal output
29
I2C. CLK
I
IIC clock input from master control
30
I2C. DATA
I
IIC data input from master control
31
DATA1O
O
Serial data output to the FLASH writer
32
DATA1I
I
Serial data input from the FLASH writer
33
CLK1
O
Serial data transfer signal output the FLASH writer
34
RTS1
O
RTS (BUSY) signal to the FLASH writer
35
DATAO
O
Serial data output to MPEG decoder
36
DATA1
I
Serial data input from MPEG decoder
37
CLK1
O
Serial clock output to MPEG decoder
38
P. ON
I
Not used (open)
39
BUS XRDY
I
Not used (connected to +5V)
40
BUS
I
Not used (open)
41
BUS XHOLD
I
Hold signal input terminal from the FLASH writer
42, 43
BUS
I
Not used (open)
44
BUS XRD
I
Not used
45
V. SYNC
I
V sync signal input
46
BUS XWRL
O
Bus write signal output to the FLASH writer
47
LO. BOOST
I
Not used (open)
48
AUDIO MUTE
O
Not used (open)
49
LOAD OUT
I
Not used (open)
50
LOAD IN
I
Not used (open)
Discription
Click on the first or last page to see other HCD-VP700 service manuals if exist.