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– 29 –

Pin No.

Pin Name

I/O

Function

1

CMD0

I/O

2

CMD1

I/O

3

CMD2

I/O

4

CMD3

I/O

5

SACK

O

Data acknowledge output to the IIC interface controller (IC901)

6

QINT

O

Interrupt status output to the IIC interface controller (IC901)

7

VDAC-XLAT

O

Serial data latch pulse output to the video D/A converter (IC401)

8

DF-XLAT

O

Serial data latch pulse output to the D/A converter/digital filter (IC101)

9

P90/TXD

O

Transmit data output terminal    Not used (open)

10

SUBQ

I

Sub-code Q data signal input from the CXD2545Q (IC101)

11

SQCK

O

Sub-code Q data transfer clock signal output to the CXD2545Q (IC101)

12

VSS

—

Ground terminal

13

D0

I/O

14

D1

I/O

15

D2

I/O

16

D3

I/O

17

D4

I/O

18

D5

I/O

19

D6

I/O

20

D7

I/O

21

VCC

—

Power supply terminal (+5V)

22

A0

O

23

A1

O

24

A2

O

25

A3

O

26

A4

O

27

A5

O

 

28

A6

O

29

A7

O

30

VSS

—

Ground terminal

31

A8

O

32

A9

O

33

A10

O

Address signal output to the S-RAM (IC751)

34

A11

O

35

A12

O

36

A13

O

37

A14

O

38

A15

O

39

A16

O

40

A17

O

41

A18

O

42

A19

O

Address signal output terminal    Not used (open)

43

WAIT

I

Wait signal input from the MPEG audio/video decoder (IC201)

44

MD0

I

Mode selection terminal (fixed at “H”)

45

MD1

I

Mode selection terminal (fixed at “L”)

46

Φ

O

System clock signal output terminal    Not used (open)

Two-way data bus with the IIC interface controller (IC901)

Two-way data bus with the S-RAM (IC751)

Address signal output to the S-RAM (IC751)

Address signal output terminal    Not used (open)

Address signal output to the MPEG audio/video decoder (IC201) and S-RAM (IC751)

Address signal output terminal    Used for chip enable signal output to the S-RAM (IC751)

– 30 –

Pin No.

Pin Name

I/O

Function

47

STBY

I

Hardware standby signal input terminal (fixed at “H”)

48

RESET

I

Reset signal input from the IIC interface controller (IC901)    “L”: reset

49

NMI

I

Non-maskable interrupt input terminal (fixed at “H”)

50

VSS

—

Ground terminal

51

EXTAL

O

System clock output terminal (10 MHz)

52

XTAL

I

System clock input terminal (10 MHz)

53

VCC

—

Power supply terminal (+5V)

54

AS

O

Address strobe signal output to the MPEG audio/video decoder (IC201)                                        
Used for chip select signal output to the MPEG audio/video decoder (IC201)

55

RD

O

Data reading strobe signal output to the S-RAM (IC751)

56

WR

O

Data writing strobe signal output to the MPEG audio/video decoder (IC201) and S-RAM
(IC751)

57

RESO

O

Reset signal output terminal    Not used (open)

58

AVSS

—

Ground terminal (for A/D conversion)

59

TEST0

I

Setting terminal for the test (color bar mode)    Normally: “H”

60

TEST1

I

Setting terminal for the test (E-F balance mode)    Normally: “H”

61

TE

I

Setting terminal for the test (E-F balance mode)    Normally: “H”

62

SENS

I

Internal status (SENSE) signal input from the CXD2545Q (IC101)

63

DAC-SEL

I

Setting terminal of the D/A converter (fixed at “H”)

64

NPIN

I

Video system selection input from the system select switch (S9001)                                              
“L”: PAL, “H”: NTSC, Middle: AUTO

65

VSS

—

Ground terminal

66

VREQ

I

Request signal input terminal    Not used (fixed at “H”)

67

VREF

I

Reference voltage (+5V) input terminal

68

AVCC

—

Power supply terminal (for A/D conversion)

69

CHECK-LED

O

LED drive signal output for the self diagnosis indicator                                                                  
Normally: LED on (“H” output), Error: LED blinking

70

XHIRQ

I

Interruption request signal input from the MPEG audio/video decoder (IC201)

71

SCOR

I

Sub-code sync (S0+S1) detection signal input from the CXD2545Q (IC101)

72

MREQ

I

Communication request signal input from the IIC interface controller (IC901) 

73

DATA

O

Serial data output to the CXD2545Q (IC101), D/A converter/digital filter (IC101), and video
D/A converter (IC401)

74

AMUTE

O

Mute control signal output to the CXD2545Q (IC101) and D/A converter/digital filter (IC101)

75

LDON

O

Laser on/off selection signal output to the CXA1821M (IC103)    “H”: laser on

76

XLT

O

Serial data latch pulse output to the CXD2545Q (IC101)

77

SCLK

O

Serial data transfer clock signal output to the CXD2545Q (IC101)

78

CLK

O

Serial data transfer clock signal output to the CXD2545Q (IC101), D/A converter/digital filter
(IC101), and video D/A converter (IC401)

79

NR-SEL

I

Setting terminal of the video noise reduction (fixed at “H”)

80

—

—

Not used (open)

– 31 –

Pin No.

Pin Name

I/O

Function

1 to 8

P80 to P87

I

Not used (fixed at “L”)

9

TEST

I

Test terminal (fixed at “L”)

10

X2

O

Main system clock output terminal (5 MHz)

11

X1

I

Main system clock input terminal (5 MHz)

12

VDD

—

Power supply terminal (+5V)

13

XT2

O

Sub system clock output terminal    Not used (open)

14

XT1

I

Sub system clock input terminal    Not used (fixed at “H”)

15

RESET

I

Reset signal input from the master controller (IC301)    “L”: reset

16

P00

I

Inputs the boundary point control (phase fix) for CXD1854Q (IC301) (fixed at “L”)

17

P01

I

Inputs the boundary point control (phase switch) for CXD1854Q (IC301) (fixed at “L”)

18

QINT

I

Interrupt status input from the CD mechanism controller (IC701)

19 to 22

P03 to P06

I

Inputs the boundary point control (phase 0 to 3) for CXD1854Q (IC301) (fixed at “L”)

23

VDD

—

Power supply terminal (+5V)

24

AVDD

—

Power supply terminal (+5V) (for A/D conversion)

25 to 32

P10 to P17

I

Not used (fixed at “L”)

33

AVSS

—

Ground terminal (for A/D conversion)

34

CMD0

I/O

35

CMD1

I/O

36

CMD2

I/O

37

CMD3

I/O

38

P24

I

Not used (fixed at “L”)

39

P25

I

Not used (fixed at “L”)

40

VSS

—

Ground terminal

41

P26

I

Not used (fixed at “L”)

42

P27

I

Not used (fixed at “L”)

43

MREQ

O

Communication request signal output to the CD mechanism controller (IC701)

44

SACK

I

Data acknowledge input from the CD mechanism controller (IC701)

45

CDGM

I

Not used (fixed at “L”)

46

P93

I

Not used (fixed at “L”)

47

MDATA

O

Serial data output to the on screen display controller (IC271) and video noise reduction (IC301)

48

MCLK

O

Serial data transfer clock signal output to the on screen display controller (IC271) and video
noise reduction (IC301)

49

OS-XLAT

O

Serial data latch pulse output to the on screen display controller (IC271)

50

G-XLAT

O

Serial data latch pulse output terminal    Not used (open)

51

G-XRST

O

Reset signal output terminal    Not used (open)

52

CD-XRST

O

Reset signal output to the CD/video CD circuit    “L”: reset

53

CDPOW

O

Power on/off selection signal output terminal    Not used (open)

54

DOUT

O

Digital output terminal    Not used (open)

55

IIC-DATA

I/O

Communication data bus with the master controller (IC301) and fluorescent indicator tube
driver (IC601)

56

IIC-CLK

I/O

Communication data reading clock signal input or transfer clock signal output with the master
controller (IC301) and fluorescent indicator tube driver (IC601)

57 to 64

P40 to P47

I

Not used (fixed at “L”)

65

NRON

O

Video noise reduction system on/off selection signal output terminal    Not used (open)

66

LEVEL0

O

Level control signal output terminal    Not used (open)

67

LEVEL1

O

Level control signal output terminal    Not used (open)

Two-way data bus with the mechanism controller (IC701)

– 32 –

Pin No.

Pin Name

I/O

Function

68

NR-XCS

O

Chip select signal output to the video noise reduction (IC301)

69

P54

I

Not used (fixed at “L”)

70

P55

I

Not used (fixed at “L”)

71

VSS

—

Ground terminal

72

P56

I

Not used (fixed at “L”)

73

P57

I

Not used (fixed at “L”)

74 to 81

P60 to P67

I

Not used (fixed at “L”)

82 to 85

P100 to P103

I

Not used (fixed at “L”)

86 to 93

P30 to P37

I

Not used (fixed at “L”)

94 to 100

P150 to P156

I

Not used (fixed at “L”)