Sony HCD-V5500 / MHC-V5500 / MHC-V7700AV Service Manual ▷ View online
HCD-V5500
6-1.
BLOCK DIAGRAM — CD SECTION —
SECTION 6
DIAGRAMS
— 13 —
— 14 —
APC LD
AMP
RF AMP
IC103
1
2
19
3
4
5
6
RF
SUMMING
AMP
RF FQ
AMP
FOCUS
ERROR
AMP
15
TRACKING
ERROR
AMP
13
11
10
VC
BUFFER
12
VC
VC
FOCUS/TRACKING COIL DRIVE
SPINDLE/SLED MOTOR DRIVE
SPINDLE/SLED MOTOR DRIVE
IC102
1
2
4
5
T+
T–
F+
F–
19
20
16
17
10
9
12
13
M
M102
SLED
SLED
MOTOR
M
M101
SPINDLE
MOTOR
27
26
23
24
TRACKING
COIL
FOCUS
COIL
16
RF
15
MUTE
16
8
9
4
A
C
B
D
E
F
DETECTOR
1
OPTICAL PICK-UP
BLOCK (KSS-213B/S-N)
LD
DRIVE
Q101
PD
LASER
DIODE
LD
LD
POWER
INTEGRATOR
INTE-
GRATOR
28
27
26
29
RF DC
TE
SE
FE
A/D
CONVERTER
4
6
10
8
2
100
96
ASYMMETRY
CORRECTION
CORRECTION
ASY0
RF AC
ASY1
MIX
36
MIRR
DFCT
FOK
DETECTOR
DIGITAL
PLL
EFM
DEMODULATOR
CLOCK
GENERATOR
FOK
DFCT
MIRR
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM
GENERATOR
TRACKING
PWM
GENERATOR
FOCUS
PWM
GENERATOR
SLED
PWM
PWM
GENERATOR
SYNC
PROTECTOR
CLV SERVO
PROCESSOR
1B TIMS
OVERSAMPLING
FILTER
NOISE
SHAPER
TIMING
GENERATOR 1
TIMING
GENERATOR 2
DIGITAL SERVO
DIGITAL SIGNAL PROCESSOR
IC101
62
XTAL
REGISTER
DATA BUS
ERROR
CORRECTOR
D/A
DATA
PROCESSOR
79
54
MUTE
GFS
99
S STOP
+5V
S101
LIMIT
SWITCH
TFDR
TRDR
FFDR
FRDR
SRDR
SFDR
MDP
32K
RAM
ADDRESS
GENERATOR
PRIORITY
EMCODER
SERIAL/PARALLEL
PROCESSOR
PEAK
DETECTOR
SUBCODE
Q
PROCESSOR
SUBCODE
P-W
PROCESSOR
DIGITAL
OUT
70
MD2
71
DOUT
EXCK
76
SBSO
75
77
78
SUBQ
SQCK
83
SCLK
73
74
SCOR
WFCK
47
BCLK
LRCK 45
DATA
46
+5V
384BD
EXCK
SUBQ
LDON
DIGITAL
OUT
IC107
OPTICAL
SUBQ
SQCK
SCLK
ADATA
LRCK
BCLK
SCOR
86
87
88
XLT
DATA
CLK
XLT
DATA
CLK
CPU
INTERFACE
SERVO
AUTO
SEQUENCER
SENS
SENS
80
56
C2PO
SERVO
INTERFACE
MIRR
91
92
DFCT
FOK
93
81
XRST
XRST
AMUTE
39
38
C2PO
VIDEO
SECTION
B
(Page 15 )
• SIGNAL PATH
: CD
: DIGITAL OUT
: VIDEO
: CD
: DIGITAL OUT
: VIDEO
1
HCD-V5500
6-2.
BLOCK DIAGRAM — VIDEO SECTION —
— 15 —
— 16 —
RGB-YUV
CONV.
TIMING
GEN.
NOISE
REDUSER
YUV-RGB
CONV.
60
67
51
58
1
4
•
6
9
11
18
71
74
•
76
80
63
70
1
4
•
6
9
11
18
MEMORY
CONT.
DRAM
IF
29
30
31
98
100
97
DCLKI
Y
C
Y
C
NOISE REDUCTION
IC301
DEMPX, LEVEL
TRANSLATOR
&
INTERPOLTATOR
VIDEO
POSTPROCESSOR
&
SYNC GENERATOR
LPF
LPF
DELAY
MODULATOR
SYNC
SLOPE
GEN.
CLOSED
CAPTION
ENCODER
SIO & I
2
O-BUS
CONT.
SUB
CARRIER
GEN.
SYNC GEN.
&
TIMING CONT.
49 50
48
59 60
62
55
57
51
1/2
56
XRST
DCLK
HSYNC
VSYNC
DCLK
XVRST
FID
VSYNC
HSYNC
VDAC-XLAT
CLK
DATA
3
4
5
6
X401
27MHz
CT401
13.5MHZ
CLOCK GENARATOR
IC402
Y, C/Y, U, V
SELECTOR
&
INTER-
POLATOR
24
29
32
5
3
1
3
2
7
7
1
4
3
V
Y
C
10BIT VIDEO D/A CONVERTER
IC401
5
7
VIDEO AMP
IC451
Y/C AMP
IC452
J603
Q601
J601
IC601
SELECTOR
S VIDEO OUT
MONITOR OUT
VIDEO IN
NR-XCS
MCLK
MDATA
MDATA
MDATA
RESET
OS-XLAT
MCLK
MCLK
OUTPUT
CONT.
4
3
2
1
8
OSD
IC271
VIDEO
RAM
DATA INPUT
SHIFT
RESISTOR
SYNC
CONT.
DATA
SEL.
DISPLAY
POSITION
CONT.
18
17
16
15
19
20
OSC
1
5
CK 1/2 Q
6.75MHz
DCLK
HSYNC
VSYNC
XOSDEN
OSD R
OSD G
OSD B
CLOCK
GENERATOR
IC272
97
95
92
93
94
89
56
57
58
59
118
HSYNC
XSGRST
VSYNC
FID
DCLK
XOSDEN
XOSDEN
OSD B
OSD G
OSD R
XRST
MPEG
VIDEO
VIDEO
DECODER
MPEG
SYSTEM
DECODER
CD-ROM
DECODER
MPEG
AUDIO
DECODER
112
111
110
109
103
100
101
102
11
12
13
14
15
9
8
7
6
5
2
3
BUFFER
IC501 (1/2)
HOST INTERFACE
117
115
116
114
EACH CIRCUIT BLOCK
D-RAM INTERFACE
34
30
15
16
31
5 6
• •
•
119 120
7–13 16
•
17–21 23 24 32 33
•
•
•
•
38–43 46–55
•
X202
28.63636MHz
106
107
X201
45.1584MHz
XTL0O
XTL01
XTL2O
XTL2I
MPEG DECODER
IC201
18–21 24–28
•
27
20
22
55
2–10 21 23–25
•
•
•
2–5 7–10 35–38 40–43
•
•
LCAS
UCAS
W
RAS
A8
A0
DQ16
DQ1
WE
CE1
OE
A12
A0
I/O8
I/O1
D-RAM
IC251
S-RAM
IC751
D0
D7
A0
A3
XHCS
XWR
XHDT
XHIRQ
•
11–13 15–19
8
10
9
6
1
2
11
12
13
XTCS
IC772
41
54
56 43 70
7 8
21–29 • 31–35
13 – 20
37
35
68
49
48
47
34
35
36
37
44
18
43
1
2
3
4
5
6
72
64
CMD0
CMD1
CMD2
CMD2
CMD3
SACK
QINT
MREQ
QINT
MREQ
MDATA
MCLK
OS-XLAT
NR-XCS
73
78
74
11
10
77
76
DATA
CLK
AMUTE
AMUTE
SQCK
SUBQ
SCLK
XLT
SCLK
XLT
CMD0
CMD1
CMD2
CMD2
CMD3
SACK
QINT
MREQ
NPIN
75
71
62
48
LDON
SCOR
SENS
RESET
SENS
RESET
384FS
DATA
CLK
CLK
AMUTE
SQCK
SUBQ
SCLK
SUBQ
SCLK
XLT
LDON
SCOR
SENS
XRST
SCOR
SENS
XRST
PAL
AUTO
NTSC
S601
SYSTEM SELECT
52
51
X701
10MHz
EXTAL
XTAL
11
10
52
X901
5MHz
X2
CD-XRST
X1
VDAC-XLAT
DF-XLAT
WAIT
WR
XHIRQ
AS
A17
A18
RD
A12
A0
D7
D0
MECHA CONTROL
IC701
56
55
15
IIC INTERFACE
IC901
RESET
IIC-DATA
IIC-CLK
B
CD
SECTION
(Page 14 )
B
CD
SECTION
(Page 14 )
16
BCK
ADATA
LRCK
LRCK
C2PO
384FS
ADATA
LRCK
LRCK
BCLK
4
16
IC501
(2/2)
DATA
CLK
AMUTE
384FS
11
6
3
11
27
25
21
22
16
18
12
10
3
4
5
2
13
4
1
BUFFER
IC181
XRST
6
INPUT
PLM
D/A
CONV.
MODE
MUTE
CIRCUIT
ADATA
384FS
LRCK
BCLK
DATA
CLK
CLK
DF-XLAT
AMUTE
TIMING
CIRCUIT
CLOCK
GENERATOR
1
IIC-CLK
IIC-DATA
XRST
L CH
CD FUNC
A
MAIN
SECTION
(Page 17)
2
3
1
6
7
R CH
ACTIVE LPF
IC102
X101
33.8688MHz
DIGITAL FILTER & D/A CONVERTER
IC101
• R CH: Same as L ch
• SIGNAL PATH
• SIGNAL PATH
: VIDEO
: Y
: CHROMA
: CD
: Y
: CHROMA
: CD
Y0-Y7
C0-C7
INT
40
5
4
3
IC771
HCD-V5500
6-3.
BLOCK DIAGRAM — DECK/SYSTEM CONTROL SECTION —
6-4.
CIRCUIT BOARDS LOCATION
— 17 —
— 18 —
— 19 —
CONNECTOR BOARD
SENSOR BOARD
MOTOR BOARD
CD PANEL BOARD
TC (A) BOARD
TC (B) BOARD
LEAF SWITCH BOARD
TC PANEL BOARD
AUDIO BOARD
MAIN BOARD
RESISTOR BOARD
MOTOR (SLIDE) BOARD
MOTOR (TURN) BOARD
BD BOARD
VIDEO BOARD
VIDEO IN BOARD
2
6
7
12
14
11
15
RECT
Q901-904
REG
IC851
REG
IC853
REG
Q852
REG
IC852
Q104
Q102
SWITCH
Q103
SWITCH
Q106
-REG
Q855
PB(L)
LEVEL
REC
BIAS
BIAS
TRAP
R CH
R CH
R CH
BIAS
OSC
OSC
Q621,622
PB EQ
AMP
IC611
3
1
RV341
Q623
+7.5V
C331,L331
ERASE
HEAD
REC/PB
HEAD
(B DECK)
HRPE101
REC/PB
HEAD
(A DECK)
HP101
RV311
R CH
PB(L)
LEVEL
PB EQ
AMP
IC601
5
7
RV301
IC602
REC/PB SWITCH
REC
EQ
BIAS
SW
DOLBY
B
NORM
CROM
REC(L)
LEVEL
LEVEL
RV401
PB A/B
IC401
DOLBY NR/REC EQ AMP
37
6
8
12
14
16
17
18
19
20
13
15
87
88
89
90
91
92
93
80
79
78
ROTARY
ENCODER
S851
97
DRIVE
Q201-204
LED
Q219,220
2
7
D201-210
FUNCTION
KEY
S251-266
73
72
70
65
53
49
41
DRIVE
Q205-218
LED
D211-227
FUNCTION
KEY
S270-282
RESET
IC103
28
MOTOR
SWITCH
CAPSTAN
SWITCH
Q410,411
M
SWITCH
Q409
Q405,408
SPEED
CONTROL
Q651
SPEED
(NOMAL)
TAPE
SPEED
(HIGH)
(HIGH)
TAPE
M
2
7
6
3
MOTOR DRIVE
IC701
OUT2
OUT1
IN2
IN1
M
61
60
M701
TURN
MOTOR
4
7
2
10
OUT2
OUT1
R IN
F IN
M
64
63
M801
SLIDE
MOTOR
MOTOR DRIVE
IC801
1
2
3
4
2
4
A
B
70
120
PB
REC
DOL
PAS
PB
REC
11
29
28
22
A7.5V
10
9
B CrO2
DET
S1008
A CrO2
DET
S1005
NORM/HIGH
NORM/CROM/METAL
BIAS ON/OFF
RM ON/OFF
NR ON/OFF
REC PB/PASS
LM ON/OFF
A120/70
IC703
L CH
VIDEO
SECTION
IIC DATA
IIC CLK
XRST
CD FUNC
DISC
D +5V
A +5V
+5V
A +7.5V
+7V
+12V
-7.5V
CD L
REC L
PB L
IIC DATA
IIC CLK
AC
AC
SYSTEM
CONTROL1
CNB108
TO STR-W550
CNP701
IC101
SYSTEM CONTROL
46
15
29
CD POWER
IIC DATA
IIC CLK
XRST
CD FUNC
RESET
LED1
LED6
KEY A
3
1
+5V
KEY B
LED20
DISC SENS
TBL SENS
A PLAY SW
75
76
11
10
30
94
Q701
SENSOR
IC702
TABLE
SENSOR
X1
X2
X101
5MHz
PB A/B
OPEN SW
S801
EQ H/N
BIAS
REC MUTE
NR ON/OFF
R/P PASS
LM ON/OFF
OUT OPEN
VZ
IN1
IN2
81
96 TC RELAY
TBL R
TBL L
LOAD IN
LOAD OUT
CAPSTAN
MOTOR
M1
TRIGGER
MOTOR
M2
A HALF SW
26
A SHUT
S1001
A PLAY
+5V
+5V
S1004
A HALF
S1007
B HALF
S1009
REC B
REC B
S1006
REC A
REC A
ROTATION
DET A
Q1001
+5V
B HALF SW
B PLAY SW 95
S1002
B PLAY
+5V
27
B SHUT
+5V
ROTATION
DET B
Q1002
TRIGGER
MOTOR DRIVE
IC402
TRG LOW
B TRG
A TRG
CAP M ON/OFF
CAP M H/L
OUT1
OUT2
2
10
4
6
5
85
84
83
86
82
.
.
LED7
.
.
.
.
E1
E2
E3
16
RV652
RV651
Signal path
: CD
: PB(DECK A)
: PB(DECK B)
: REC(DECK B)
55
56
57
A
(Page 16 )
37
Q105
D +5V
HCD-V5500
6-17. IC BLOCK DIAGRAMS
— 53 —
— 54 —
IC101
CXD2545Q
IC103
CXA1821M-T6
IC201
CXD1852AQ
IC101
CXD8567AM
26
27
28
29
30
31
32
33
34
35 36
37
38
39 40 41 42
43
44 45
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
92 91
90
89
88
87
86
85 84 83
93
94
95
96
97
98
99
100
SLED PWM
GENERATOR
TRACKING PWM
GENERATOR
FOCUS PWM
GENERATOR
GENERATOR
PWM GENERATOR
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
CLV
PROCESSOR
CPU
INTERFACE
NOISE
SHAPER
18-TIMES
OVER SAMPLING
FILTER
CPU
INTERFACE
CPU
INTERFACE
ADDRESS
GENERATOR
CPU
INTERFACE
PRIORITY
ENCODER
ENCODER
CPU
INTERFACE
ERROR
CORRECTOR
CPU
INTERFACE
TIMING
GENERATOR 2
MIRR
DFCT
FOK DETECTOR
32K RAM
REGISTER
D/A
DIGITAL
PROCESSOR
TIMING
GENERATOR 1
SYNC
PROTECTOR
DIGITAL
OUT
SUBCODE
P-W
PROCESSOR
SUBCODE
Q
PROCESSOR
DIGITAL
PLL
VARI-PITCH
DOUBLE SPEED
CPU
INTERFACE
EFM
DEMODULATOR
SERIAL
PARALLEL
PROCESSOR
CPU
INTERFACE
ASYMMETRY
CORRECTION
CORRECTION
1
2
2
3
4
5
5
6
7
8
9
10
11
20
19
18
17
16
15
14
13
12
21
22
23
24
25
46 — 50
61
|
51
PEAK
DETECTOR
CLOCK
GENERATOR
MUX
A/D
CONVERTER
SWITCH
&
BUFFER
SERVO
AUTO
SEQUENCER
SERVO
MICRO PROGRAM
INTERFACE
RFC
ADIO
AVSS
IGEN
AVDD
VCKI
VPCO
PDO
TES3
TES2
DVSS
TEST
VCO1
VCO0
SRON
SRDR
SRDR
SFON
TFDR
TRON
TRDR
TFON
FFDR
FRON
FRDR
FRDR
FFON
RFDC
TE
SE
FE
VC
FILO
FILI
PCO
CLTV
AVSS
RFAC
BIAS
ASYI
ASYO
AVDD
ADD
ASYE
PSSL
WDCK
LRCK
XTAI
XTAO
XTSL
DVSS
FSTI
FSTO
D OUT
MD2
C16M
C4M
SCOR
WFCK
EMPH
SBSO
EXCK
SQSO
SQCK
MUTE
SENS
XRST
DIRC
SCLK
DFSW
ATSK
DATA
XLAT
CLOK
COUT
ADD
MIRR
DFCT
FOK
FSW
MON
MDP
MDS
LOCK
SSTP
SFDR
4
3
DA01
|
DA11
DA16
|
DA12
1
INIT
2
3
4
5
6
7
8
9
10
11
12
13
14
D Vdd 2
SYSM
L1 (+)
ATT
A Vdd L
SHIFT
L2 (+)
LATCH
A Vss L
256FSO
X Vss
TEST1
512IN
D Vss
X OUT
MCKSEL
X Vdd
XBCK
A Vss R
DATA
R2 (+)
LRCK
A Vdd R
MUTE L
R1 (+)
MUTE R
D Vdd 1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
MODE
S/P
ATT
IIR
FIR3
FIR2
FIR1
PLM
PLM
MUTE
CIRCUIT
CLOCK
GENERATOR
AC
DITHER
DC
DITHER
3RD ORDER
NOISE SHAPER
SAMPLE
HOLD (X1)
TIMING CIRCUIT
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
LD
VCC
VCC
PD
LD ON
A
LC/PD
B
RFE
C
RFO
D
FE
VEE
FE BIAS
F
TE
E
VC
VC
VC BUFFER
TRACKING ERROR AMP
FOCUS ERROR AMP
RF EQ AMP
APC LD AMP
RF SUMMING AMP
EI
EO
VEE
VCC
VCC
VC
VC
VC
VC
VC
VC
VC
VEE
VEE
VEE
VREF
VSS
XTLOO
XTLO1
VDD
HA2
HA3
HD0
HD1
HD2
HD3
HD4
HD5
HD6
VDD
VSS
HD7
MA3
MA4
MA2
MA5
MA1
VSS
MA6
MA0
BC
TCKI
TDI
TENAI
TDO
VST
HA1
CLOCK
HA0
XRST
XHIRQ
XRW
XHDT
XHCS
DOIN
BCKI
DATI
LRCI
C2PO
VDD
XTL2I
XTL2O
VSS
VDD
FSXI
BCKO
LRCO
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DATO
99
DOUT
98
CLK0O
97
XSGRST
96
CSYNC
95
CBLNK/FSC
94
FID/FHREF
93
VSYNC
92
HSYNC
91
VSS
31 VSS
32 MA7
33 MA8
34 XRAS
35 XMWE
36 XCAS2/MA9
37 XCAS0
38 MD7
39 MD8
40 MD6
41 MD9
42 MD5
43 MD10
44 VDD
45 VSS
46 MD4
47 MD11
48 MD3
49 MD12
50 MD2
51 MD13
52 MD1
53 MD14
54 MD0
55 MD15
56 XOSDEN
57 OSDB
58 OSDG
59 OSDR
60 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VDD
DCLK
B/Cb7
B/Cb6
B/Cb5
B/Cb4
B/Cb3
B/Cb2
B/Cb1
B/Cb0
G/Y7
G/Y6
G/Y5
G/Y4
G/Y3
VSS
VDD
G/Y2
G/Y1
G/Y0
R/Cr7
R/Cr6
R/Cr5
R/Cr4
R/Cr3
R/Cr2
R/Cr1
R/Cr0
XVOE
VSS
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VIDEO POSTPROCESSOR
&
SYNC GENERATOR
CLOCK
RESET
CLOCK
TEST
HOST
INTERFACE
CD-ROM
DECODER
D-RAM
INTERFACE
MPEG
SYSTEM
DECODER
MPEG
AUDIO
DECODER
MPEG
VIDEO
VIDEO
DECODER
EACH
CIRCUIT
BLOCK
CIRCUIT
BLOCK
Click on the first or last page to see other HCD-V5500 / MHC-V5500 / MHC-V7700AV service manuals if exist.