Sony HCD-V5500 / MHC-V5500 / MHC-V7700AV (serv.man2) Service Manual ▷ View online
— 63 —
Pin No.
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
I/O
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
O
O
—
O
O
O
O
O
O
O
O
—
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
—
I
I
I
I
—
I
Description
[MSB]
R (Cb/Cr) output 0–7
[LSB]
Power supply (+5V)
[MSB]
G (Y) output 0–7
[LSB]
Power supply (+5V)
[MSB]
B output 0–7 (Not used)
[LSB]
Ground
H SYNC output (Not used)
V SYNC output (Not used)
Composit blanking output (Not used)
Composit SYNC output (Not used)
Profile cooperation effect level control
Profile cooperation effect level control
Test pin (Connect to ground)
Test pin (Connect to +5V)
Profile cooperation correction band control
Matrix select Y/C, RGB (Connect to ground)
Profile cooperation correction band control
Noise reducer on/off (L: off, H: on)
Noise reducer level select
0: weak –3: strong (Not used)
NR feedback coefficient user processor select (Connect to +5V)
Power on reset
Ground
Composit SYNC input (Connect to ground)
Composit blanking input (Connect to +5V)
V SYNC input
H SYNC input
Power supply (+5V)
Dot clock input (13.5MHz)
Pin Name
C/RO0
C/RO1
C/RO2
C/RO3
C/RO4
C/RO5
C/RO6
C/RO7
VDD
Y/GO7
Y/GO6
Y/GO5
Y/GO4
Y/GO3
Y/GO2
Y/GO1
Y/GO0
VDD
BO0
BO1
BO2
BO3
BO4
BO5
BO6
BO7
VSS
HSYO
VSYO
CBLO
CSYO
HAPGAIN0
HAPGAIN1
TEST
TEN
HAPBPF0
IFSEL 1
HAPBPF1
NRON
LEVEL 0
LEVEL 1
FNR UFRZ
XRST
VSS
CSYI
CBLI
VSYI
HSYI
VDD
DCLKI
— 64 —
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I
I
I
I
—
I
I
I
I
—
I
I
I
I
I
I
I
I
—
O
I
—
—
O
I
I
—
—
O
—
—
O
O
—
O
O
I
I
I
—
I
—
I
I
Description
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE”=“0”, serve as input pins for multiplexed Y, Cb, Cr signals.
When control register bit “PIF MODE”=“1”, serve as input pins for Y signal.
Digital ground
8-bit pixel data input pins (PD0 to 7).
When control register bit “PIF MODE”=“0”, serve as input pins for multiplexed Y, Cb, Cr signals.
When control register bit “PIF MODE”=“1”, serve as input pins for Y signal.
Digital power supply
8-bit pixel data input pins/test data bus.
When control register bit “PIF MODE”=“0”, these input pins cannot be used.
When control register bit “PIF MODE”=“1”, serve as input pins for multiplexed Cb, Cr signals.
In the test mode, used for internal circuit test data bus.
The test mode is allowed to use only for device vendors.
Digital ground
Reference current output pin. Connect a resistor
×
16 times (“16R”) of the output resistance value “R”
Voltage reference input pin. Sets the output full-scale value
Analog power supply
Analog ground
10-bit D/A converter output.
When control register bit “YC/YUV”=“1”, outputs the composite signal.
When control register bit “YC/YUV”=“0”, outputs the color difference (V) signal.
Connect to Vss with an approx. 0.1
µ
F capacitor
Connect to AVDD with an approx. 0.1
µ
F capacitor
Analog power supply
Analog ground
10 bit D/A converter output. (Luminance (Y) signal output.)
Analog power supply
Analog ground
10-bit D/A converter output.
When control register bit “YC/YUV”=“1”, outputs the chroma (C) signal.
When control register bit “YC/YUV”=“0”, outputs the color difference (U) signal.
Test data bus. In the test mode, used for internal circuit test data bus.
The test mode is allowed to use only for device vendors (Not used).
Digital power supply
Test data bus. In the test mode, used for internal circuit test data bus.
The test mode is allowed to use only for device vendors (Not used)
Test mode control input pin. Pulled-up.
When these pins are “H”, CXD1913Q is not in the test mode.
The test mode is allowed to use only for device vendors
Digital ground
Test mode reset input pin. During power on/reset, set to “L” for more than 40 clocks (SYSCLK) (Not used)
Digital power supply
Test mode control input pin. (Not used)
Pin Name
Y7
Y6
Y5
Y4
VSS
Y3
Y2
Y1
Y0
VDD
C7
C6
C5
C4
C3
C2
C1
C0
VSS
IREF
VREF
AVDD1
AVSS1
COMPO
VB
VG
AVDD2
AVSS2
YOUT
AVDD3
AVSS3
COUT
TD10
VDD
TD9
TD8
XTEST1
XTEST2
XTEST3
VSS
TRST
VDD
TDI
TMS
• IC401 10 BIT VIDEO D/A CONVERTER (CXD1913Q)/VIDEO board
— 65 —
Pin No.
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
I/O
I
O
—
I
I
I
I
I
—
I
I
I
O
—
O
O
O
O
—
I
Description
Test mode control input pin. Fix at “H”
Test data bus pin. (Not used)
Digital ground
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the SI serial data input pin.
When the XIICEN pin is “L”, sets into the I
2
C-BUS mode, and becomes the SDA input/output pin
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the SCK serial clock input pin.
When the XIICEN pin is “L”, sets into the I
2
C-BUS mode, and becomes the SCL input pin
The functions of this pin are selected by Pin 64 XIICEN. Pulled-up.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the XCK chip select input pin.
When the XIICEN pin is “L”, sets into the I
2
C-BUS mode, and becomes the SA slave address selection input
signal which selects the I
2
C-BUS slave address
Active “L” vertical sync reset input pin. Pulled-up.
Used for synchronizing external vertical sync and internal vertical sync.
When XVRST is “L”, the internal digital sync generator is reset according to the F1 state
Field ID input pin.
When externally synchronizing with the XVRST signal, the field to be reset is determined by this signal.
“H” indicates the first field.
“L” indicates the second field
Digital power supply
Test mode control input pin. Pulled-up.
When these pins are “H”, CXD1913Q is not s test mode.
The test mode is allowed to use only for device vendors
System reset input pin when active “L”.
During power on/reset, set to “L” for more than 40 clocks (SYSCLK)
System clock input pin.
To generate the correct sub carrier frequency, precisely 27MHz is required
13.5MHz pixel data clock output pin. This clock is obtained by 1/2 frequency-dividing SYSCLK.
Used only in the 16-bit pixel data mode
Digital ground
V.sync signal output
H.sync signal output
The functions of this pin are selected by Pin 64 XIICEN.
When the XIICEN pin is “H”, sets into the SONY SIO mode, and becomes the S0 serial-out output pin.
When the XIICEN pin is “L”, this pin is not used and sets into high impedance (Not used)
Field ID output.
When control register bit “FDS”=“1”, “L” indicates the first field and “H” indicates the second field.
When control register bit “FDS”=“0”, “H” indicates the first field and “L” indicates the second field
Digital power supply
Serial interface mode selection input pin. Pulled-up.
When “L”, Pins 48 to 50, and 61 set into the I
2
C-BUS mode.
When “H”, Pins 48 to 50, and 61 set into the SONY SOP mode
Pin Name
TCK
TDO
VSS
SI
SCK
XCS
XVRST
F1
VDD
XTEST4
XRST
SYSCLK
PDCLK
VSS
VSYNC
HSYNC
SO
FID
VDD
XIICEN
— 66 —
• IC701 MECHANISM CONTROL (HD6433032SK12F)/VIDEO board
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13 to 20
21
22 to 29
30
31 to 35
36 to 39
40, 41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
I/O
I/O
I/O
I/O
I/O
O
O
O
O
—
I
O
—
I/O
—
O
—
O
O
O
O
I
I
I
O
I
I
I
—
I
I
—
O
O
O
O
—
I
I
I
I
I
I
—
I
I
Description
Input/output terminal exchanging data bus 0 with IIC interface (IC901)
Input/output terminal exchanging data bus 1 with IIC interface (IC901)
Input/output terminal exchanging data bus 2 with IIC interface (IC901)
Input/output terminal exchanging data bus 3 with IIC interface (IC901)
Outputs command acknowledge to IIC interface (IC901)
Outputs command output pulses to IIC interface (IC901)
Serial data latch pulse output to Video D/A converter (IC401)
Serial data latch pulse output to Audio D/A converter (IC101)
Not used
Sub Q 80bit input (CXD2545Q)
SQSO readout clock output (CXD2545Q)
Ground
Data bus input/output (IC201, 751)
Connect to the power supply (+5V)
Address bus output (IC201, 751)
Ground
Address bus output (IC201, 751)
Address bus output (Not used)
Addres bus output (IC772)
Address bus output (Not used)
BUS control wait input (IC201)
Operation mode setting terminal (Connected to +5V)
Operation mode setting terminal (Connected to ground)
System clock output (Not used)
Shifts to the hardware standby mode when the standby terminal becomes “Low”.
(Unable to use H level fixed) (Connected to +5V)
Set into reset when the reset input pin becomes “Low”. (IC901)
Requests mask disable interruption. (Unable to use H level fixed) (Connected to +5V)
Ground
Connected to the Crystal oscillator. The EXTAL pin is also able to input external clocks. (10 MHz)
Connected to the Crystal oscillator. (10 MHz)
Power supply (+5V)
When the address strobe pin is “Low”, indicates that address outputs on the address bus are valid. (IC772)
When the read pin is “Low”, indicates that the external addresses space is in the read state. (IC201, 751)
When the read pin is “Low”, indicates that the external addresses space is in the write state and the data bus are
valid. (IC201, 751)
Reset output (Not used)
A/D converter (Pin62-69) ground
Color-bar test input (“L” = test)
AFADJ test input (“L” = test)
ADJ test input (“L” = test)
Internal state (SENSE) monitor input (CXD2545Q)
Audio D/A converter select mode setting terminal (Connected to +5V)
NTSC/PAL output mode setting terminal (0V : NTSC, 1.5V : AUTO, 3V : PAL)
Ground
Not used
A/D converter (Pin62-69) reference voltage input (Connected to +5V)
Pin Name
CMD0
CMD1
CMD2
CMD3
SACK
QINT
VDAC-XLAT
DF-XLAT
P90/TXD
SUBQ
SQCK
VSS
D0 to D7
VCC
A0 to A7
VSS
A8 to A12
A13 to A16
A17, A18
A19
WAIT
MD0
MD1
φ
STBY
RESET
NM1
VSS
EXTAL
XTAL
VCC
AS
RD
WR
RESO
AVSS
TEST0
TEST1
TE
SENS
DAC-SELECT
NPIN
VSS
VREQ
VREF
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