Sony HCD-RV777D / HCD-RV888D / HCD-RV999D / MHC-RV777D / MHC-RV888D / MHC-RV999D Service Manual ▷ View online
41
HCD-RV777D/RV888D/RV999D
• IC207 ZIVA5X-C2F (DVD SYSTEM PROCESSOR) (DMB07 Board (7/8))
Pin No.
Pin Name
I/O
Pin Description
1
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
2
HA1
I/O
Address bus signal input from/output to bus interface IC.
3 to 11
HAD15 to HAD7
I/O
Data bus (address signal multiplexed) signal input from/output to bus interface IC.
12
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
13
GNDP
—
Ground pin (I/O signal)
14 to 19
HAD6 to HAD1
I/O
Data bus (address signal multiplexed) signal input from/output to bus interface IC.
20
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
21
GNDP
—
Ground pin (I/O signal)
22
HAD0
I/O
Data bus (address signal multiplexed) signal input from/output to bus interface IC.
23
HDTACK
I/O
Not used in this set. (Fixed at H.)
24
HIRQ0
I
Not used in this set. (Fixed at H.)
25
WEH.UDS
I/O
Host upper data strobe signal input from/output to programmable ROM IC.
26
WEL.LDS
I/O
Not used in this set. (Open)
27
HREAD
I/O
Read/write strobe signal input from/output to programmable ROM IC.
28
GPIO0(1)
I/O
Jig detection port
29
GND
—
Ground pin (inside core)
30
VDD
—
Power supply pin (+1.8 V) (inside core)
31
GND25
—
Ground pin (SDRAM I/O signal)
32
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
33 to 42
MA9 to MA0
O
SDRAM address bus signal output to 128 Mbit SD-RAM IC.
43
GND25
—
Ground pin (SDRAM I/O signal)
44
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
45, 46
MA10, MA11
O
SDRAM address bus signal output to 128 Mbit SD-RAM IC.
47, 48
BA1, BA0
O
SDRAM bank select signal output to 128 Mbit SD-RAM IC.
49
MCS0
O
SDRAM chip select signal output to 128 Mbit SD-RAM IC.
50
MCS1
O
Not used in this set. (Open)
51
MRAS
O
SDRAM row address strobe signal output to 128 Mbit SD-RAM IC.
52
MCAS
O
SDRAM column address strobe signal output to 128 Mbit SD-RAM IC.
53
MWE
O
SDRAM write enable signal output to 128 Mbit SD-RAM IC. (H: read, L: write)
54
GND25
—
Ground pin (SDRAM I/O signal)
55
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
56
MCLK
O
SDRAM clock signal output to 128 Mbit SD-RAM IC.
57 to 60
MD0 to MD3
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
61
GND25
—
Ground pin (SDRAM I/O signal)
62
MDQM0
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
63
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
64 to 71
MD4 to MD11
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
72
GND25
—
Ground pin (SDRAM I/O signal)
73
MDQM1
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
74
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
75 to 78
MD12 to MD15
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
79
GND
—
Ground pin (inside core)
80
VDD
—
Power supply pin (+1.8 V) (inside core)
81 to 84
MD16 to MD19
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
85
GND25
—
Ground pin (SDRAM I/O signal)
86
MDQM2
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
87
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
88 to 95
MD20 to MD27
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
96
GND25
—
Ground pin (SDRAM I/O signal)
97
MDQM3
O
Byte read/write mask signal output to 128 Mbit SD-RAM IC.
98
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
99 to 102
MD28 to MD31
I/O
SDRAM data input from/output to 128 Mbit SD-RAM IC.
42
HCD-RV777D/RV888D/RV999D
Pin No.
Pin Name
I/O
Pin Description
103
GND25
—
Ground pin (SDRAM I/O signal)
104
VDD25
—
Power supply pin (+3.2 V) (SDRAM I/O signal)
105
VCLK
I/O
Not used in this set. (Open)
106
XCK_I/O_SEL
I/O
Not used in this set. (Open)
107
VS
O
S1 signal output
108
I/P SW
O
I/P select switch signal output
109
CDSEL
O
CD-DA select signal output
110
MREQ
O
Audio muting signal output to sound control IC.
111
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
112
GNDP
—
Ground (I/O signal)
113
MDI
O
Serial data output to 2CH DAC IC (HCD-RV777D) and D/A converter IC (HCD-
RV888D/RV999D).
114
MC
O
Serial data clock signal output to 2CH DAC IC (HCD-RV777D) and D/A converter IC
(HCD-RV888D/RV999D).
115
ML
O
Latch enable signal output to 2CH DAC IC (HCD-RV777D) and D/A converter IC
(HCD-RV888D/RV999D).
116
HIRQ2
I
Busy signal input from EEPROM IC.
117
VDAC_4B
—
Video DAC bias bit 4 (Connect to ground.)
118
VDAC_VDD4
—
Power supply pin (+3.3 V) (Video DAC 4)
119
VDAC_4
O
VDAC output 4
120
VDAC_3B
—
Video DAC bias bit 3 (Connect to ground.)
121
VDAC_VDD3
—
Power supply pin (+3.3 V) (Video DAC 3)
122
VDAC_3
O
VDAC output 3
123
VDAC_2B
—
Video DAC bias bit 2 (Connect to ground.)
124
VDAC_VDD2
—
Power supply pin (+3.3 V) (Video DAC 2)
125
VDAC_2
O
VDAC output 2
126
VDAC_1B
—
Video DAC bias bit 1 (Connect to ground.)
127
VDAC_VDD1
—
Power supply pin (+3.3 V) (Video DAC 1)
128
VDAC_1
O
VDAC output 1
129
VDAC_0B
—
Video DAC bias bit 0 (Connect to ground.)
130
VDAC_VDD0
—
Power supply pin (+3.3 V) (Video DAC 0)
131
VDAC_0
O
VDAC output 0
132
VDAC_DVSS
—
Ground pin (Video DAC digital system)
133
VDAC_DVDD
—
Power supply pin (+3.2 V) (Video DAC digital system)
134
VDAC_REFVDD
—
Power supply pin (+3.3 V) (Video DAC reference)
135
VDAC_REF
I
Reference voltage input (for Video DAC)
136
VDAC_REFVSS
—
Ground pin (Video DAC reference)
137
XVSS
—
Ground pin (crystal oscillator)
138
XOUT
O
Not used in this set. (Open)
139
XIN
I
Crystal oscillation signal input
140
XVDD
—
Power supply pin (+3.2 V) (crystal oscillator)
141
AVSS2
—
Ground pin (analog PLL)
142, 143
AVDD2, AVDD1
—
Power supply pin (+3.2 V) (analog PLL)
144
AVSS1
—
Ground pin (analog PLL)
145
VDD
—
Power supply pin (+1.8 V) (inside core)
146
GND
—
Ground pin (inside core)
147
XCK
O
Audio system clock signal output to 2CH DAC IC (HCD-RV777D) and D/A converter
IC (HCD-RV888D/RV999D).
148
LRCK
O
LRCK signal output to 2CH DAC IC (HCD-RV777D) and D/A converter IC (HCD-
RV888D/RV999D).
149
BCK
O
BCK signal output to 2CH DAC IC (HCD-RV777D) and D/A converter IC (HCD-
RV888D/RV999D).
150
DATA0(DM)
O
Audio data (down mix signal) output to D/A converter IC (HCD-RV888D/RV999D).
43
HCD-RV777D/RV888D/RV999D
Pin No.
Pin Name
I/O
Pin Description
151
DATA1(FLR)
O
Audio data (front L/R signal) output to 2CH DAC IC (HCD-RV777D) and D/A
converter IC (HCD-RV888D/RV999D).
152
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
153
GNDP
—
Ground pin (I/O signal)
154
DATA2(SLR)
O
Audio data (rear L/R signal) output to D/A converter IC (HCD-RV888D/RV999D).
155
DATA3(CSW)
O
Audio data (center/subwoofer signal) output to D/A converter IC (HCD-RV888D/
RV999D).
156
IEC958
O
S/PDIF signal output
157
DAI_DATA
I
Not used in this set. (Open)
158
DAI_BCK
I
Not used in this set. (Open)
159
DAI_LRCK
I
Not used in this set. (Open)
160
I2C_CL
I/O
I2C clock bus signal input from/output to mechanism control IC.
161
I2C_DA
I/O
I2C data bus signal input from/output to mechanism control IC.
162
CS(ZIVA_E2P)
O
Chip select signal output to EEPROM IC.
163
RXD1
I
Serial data input from check jig
164
TXD1
O
Serial data output to check jig
165
WRITE_CTRL(ZIVA_E2P)
O
Write control signal output to EEPROM IC.
166
GNDP
—
Ground pin (I/O signal)
167
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
168 to 171
SDDATA7 to SDDATA4
I
SDBUS data input from DVD decoder IC.
172
GND
—
Ground pin (inside core)
173
VDD
—
Power supply pin (+1.8 V) (inside core)
174 to 177
SDDATA3 to SDDATA0
I
SDBUS data input from DVD decoder IC.
178
SDREQ
O
SDBUS data request signal output to DVD decoder IC.
179
SDEN
I
SDBUS data enable signal input from DVD decoder IC.
180
GNDP
—
Ground pin (I/O signal)
181
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
182
SDERROR
I
SDBUS data error signal input from DVD decoder IC.
183
SDCLK
I
SDBUS data clock signal input from DVD decoder IC.
184
HIRQ1
I
Interrupt signal input from mechanism control IC.
185
DRVCLK
I
Serial data clock signal input from mechanism control IC.
186
DRVTX
I
Serial data input from mechanism control IC and EEPROM IC.
187
DRVRX
O
Serial data output to mechanism control IC and EEPROM IC.
188
DRVRDY
I
Ready signal input from mechanism control IC.
189
VNW
—
Power supply for 5 V tolerance voltage input
190
ALE
O
Latch enable signal output for address data demux.
191
RST_SPC
O
Reset signal output to mechanism control IC.
192
INT/EXT
O
Not used in this set. (Open)
193
HCS2
O
Not used in this set. (Open)
194
HCS1
I/O
Not used in this set. (Open)
195
HCS0
O
Chip select signal output to programmable ROM IC.
196
VDDP
—
Power supply pin (+3.2 V) (I/O signal)
197
TRST
I
Reset signal input
198
TDO
O
Data output
199
TDI
I
Data input
200
TMS
I
TMS signal input
201
TCK
I
TCK signal input
202
RESET
I
ZIVA reset signal input
203
BUS CLK
I/O
Not used in this set. (Open)
204
GND
—
Ground pin (inside core)
205
VDD
—
Power supply pin (+1.8 V) (inside core)
206, 207
HA3, HA2
I/O
Address bus signal input from/output to bus interface IC.
208
GNDP
—
Ground pin (I/O signal)
44
HCD-RV777D/RV888D/RV999D
• IC701 M30620MCN-A38FPU0 (MASTER CONTROL) (MAIN Board (3/3))
Pin No.
Pin Name
I/O
Pin Description
1
S-OUT
O
Serial out signal output
2
S-CLK
O
Serial clock signal output
3
M61530-CLK
O
M61530FP clock signal output
4
SIRCS
I
Sircs signal input
5
M61530-DATA
O
M61530FP data signal output
6
M61530-DATA
O
M61530FP data signal output
7
M61537-CLK
O
M61537FP clock signal output
8
EXT.BUS-INPUT
I
External bus input with selector input (Fixed at L.)
9
PROCESSOR.MODE-SW
I
Processor mode switch signal input (Fixed at L.)
10
SUB.CLOCK-IN
I
Sub clock signal input (32.768 kHz)
11
SUB.CLOCK-OUT
O
Sub clock signal output (32.768 kHz)
12
RESET
I
System reset signal input
13
SYSTEM.CLOCK.OUT
O
System clock signal output (16 MHz)
(16M)
14
VSS
—
Ground pin
15
SYSTEM.CLOCK.IN (16M)
I
System clock signal input (16 MHz)
16
VCC
—
Power supply pin (+3.3 V)
17
PULL.UP (EVER3.3V)
I
Pull up (EVER +3.3 V)
18
RDS-INT
I
RDS clock signal input Not used in this set. (Fixed at L.)
19
NO-USE
I
Not used. (Fixed at L.)
20
AC-CUT
I
AC cut select signal input (L: ON, H: OFF)
21
RDS-DATA
I
Not used in this set. (Fixed at L.)
22
ST-MUTE
O
Stereo mute select signal output (L: OFF, H: ON)
23
STEREO
I
Stereo select signal input (L: ON, H: OFF)
24
TUNED
I
Tuned select signal input (L: ON, H: OFF)
25
ST-CE
O
Stereo chip enable signal output
26
ST-DOUT
O
Stereo data out signal output
27
ST-DIN
I
Stereo data in signal input
28
ST-CLK
O
Stereo clock signal output
29
IIC-CLK
I/O
IIC clock signal input/output
30
IIC-DATA
I/O
IIC data input/output
31
SYS-POWER
O
System power select signal output (L: OFF, H: ON)
32
SYS-RESET
O
System reset signal output
33
M-REQ
I
DAC mute request select signal input from ZIVA. (L: ON, H: OFF)
34
VIDEO-MUTE2
O
Video mute 2 select signal output (L: ON, H: OFF)
35
VIDEO-MUTE1
O
Video mute 1 select signal output (L: ON, H: OFF)
36
VIDEO-OUT-SW
O
Video out switch select signal output (L: DVD, H: other)
37
REAR-MUTE
O
Surround (rear) mute select signal output (L: ON, H: OFF)
38
CENTER-MUTE
O
Center mute select signal output (L: ON, H: OFF)
39
SWFR-MUTE
O
Sub woofer mute select signal output (L: ON, H: OFF)
40 to 44
NO-USE
O
Not used. (Fixed at L.)
45
M-RESET
O
Reset signal output
46
STANDBY-LED
O
Standby LED control signal output (L: OFF, H: ON)
47
TBL-POS
O
Table motor drive control signal output (+)
48
TBL-NEG
O
Table motor drive control signal output (–)
49
LOD-POS
O
Loading motor drive control signal output (+)
50
LOD-NEG
O
Loading motor drive control signal output (–)
51
ENCODER-SW1
I
Disc tray address signal input (Disc 1)
52
ENCODER-SW2
I
Disc tray address signal input (Disc 2)
53
ENCODER-SW3
I
Disc tray address signal input (Disc 3)
54
EJECT-SW
I
Open/close select signal input (L: open, H: close)
55
T-SENS
I
Table sensor signal input
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