Sony HCD-RV555 / MHC-RV555 Service Manual ▷ View online
53
HCD-RV555
IC101 BD3401KS2 (MAIN Board)
0
+
SI
SC
DIGITAL
CONTROL
Di-LIMITER
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
47
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
SURROUND
ATT
ATT
BUFFER
MIX
MIC MIX
VOCAL FADER
+
-
+
-
BASS MIDDLE TREBLE
BASS MIDDLE TREBLE
G
fc=100HZ
f
ALC
ALC
INPUT
SELECTOR
+
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
+
-
49
SOFT
SWITCH
+
+
-
+
-
+
TNF2
TNF1
SUR1
SUR2
LINEOUT2(R)
LINEOUT1(L)
SAOUT2
SAOUT1
CAP
MIC
GAME L
GAME R
TUNER L
TUNER R
MD L
MD R
CD L
CD R
TAPE L
TAPE R
PBNF2
PBNF1
PB OUT2
PB OUT1
TAPE A1
TAPE A2
TAPE B1
TAPE B2
RECNF2
RECNF1
REC OUT2
REC OUT1
VOLOUT2
BBNF2
BBIN2
LF1
LF2
LF3
LF4
SW OUT
FILTER
1/2 VCC
VCC
GND
VDD
ALC
VOLOUT1
TONE OUT1
TONE OUT2
AMS OUT
BNF2
BNF1
MNF1
MNF2
MOUT1
MOUT2
BOUT2
BOUT1
BBNF1
BBIN1
VIN1
VIN2
1
2
3
4
5
6
7
8
9
REC SW
P/B SW
GND
CONT
GND
VCC
P/B SW
GND
REC SW
OUTPUT BUFFER (Open Drain)
12BIT SHIFT REGESTER
12BIT STORAGE
RAGESTER
RAGESTER
CONTOROL
CIRCUIT
L. P. F
VDD
OE
SO
Q11
Q10
Q9
Q8
Q7
Q6
Q5
1
2
3
5
6
7
8
4
10
16
15
14
13
12
11
9
17
18
19
20
VSS
N.C.
DATA
CLOCK
LCH
Q0
Q1
Q2
Q3
Q4
IC201 BA3126N (MAIN Board)
IC371 BU2099FV (MAIN Board)
54
HCD-RV555
• IC Pin Function Description
• IC505 CXD1887R (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR,
• IC505 CXD1887R (DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR,
MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL ENCODER) (VMP BOARD (2/2))
Pin No.
Pin Name
I/O
Pin Description
1
VB
O
Connected to ground via a capacitor.
2
IREF
O
D/A converter reference current output
3
VRF
I
D/A converter reference voltage input
4
VG
O
Connected to the analog power supply (+2.5 V) via a capacitor.
5
XCPSIG
O
Composite/component video signal invert output (Connected to ground)
6
CPSIG
O
Composite/component video signal output
7, 8
NC
—
Not used. (Pin 7: Open, Pin 8: Fixed at “H”.)
9
V AVS2
—
Analog ground
10
IVD1
—
Power supply (+3.3 V)
11
I2C CLK
—
Not used. (Open)
12
I2C DATA
—
Not used. (Open)
13
GPIO0
I
Serial data input from the system controller
14
GPIO1
O
Serial data output to the system controller
15
GPIO2
O
Serial data transfer clock signal output to the system controller
16
GIPO3
I
Request signal input from the system controller
17
LVD1
—
Digital power supply (+2.5 V)
18
GPIO4
I
Acknowledge signal input from the system controller
19
GPIO5
O
Chip select signal output to the system controller
20, 21
GPIO6, GPIO7
—
Not used. (Open)
22
LVS1
—
Digital ground
23
GPIO8
—
Not used. (Open)
24
GPIO9
O
Frequency selection signal output
25
GPIO10
—
Not used. (Open)
26
GPIO11
O
Serial data latch pulse signal output to the digital filter
27
LVD2
—
Digital power supply (+2.5 V)
28
GPIO12
O
Control signal output to the D/A converter
29
GPIO13
O
Serial data transfer clock signal output to the digital filter and D/A converter
30
GPIO14
O
Serial data output to the digital filter and D/A converter
31
IVS1
—
Ground
32
LVS2
—
Digital ground
33
IVD2
—
Power supply (+3.3 V)
34 to 37
DRADR0 to DRADR3
O
Address signal output to the D-RAM and program ROM
38
LVD3
—
Digital power supply (+2.5 V)
39 to 45 DRADR4 to DRADR10
O
Address signal output to the D-RAM and program ROM
46
LVS3
—
Digital ground
47
IVS2
—
Ground
48
IVD3
—
Power supply (+3.3 V)
49 to 56
DRDAT0 to DRDAT7
I/O
Data bus with the D-RAM and program ROM
57
IVS3
—
Ground
58
IVD4
—
Power supply (+3.3 V)
59 to 66
DRDAT8 to DRDAT15
I/O
Data bus with the D-RAM and program ROM
67
IVS4
—
Ground
68
DRCAS
O
Column address strobe signal output to the D-RAM
69
LVD4
—
Digital power supply (+2.5 V)
70
DRCK
O
Clock signal output to the D-RAM
71
IVD5
—
Power supply (+3.3 V)
72
DRRAS
O
Row address strobe signal output to the D-RAM
73
DRWEL
O
Write enable signal output to the D-RAM
55
HCD-RV555
74
NVOEL
O
Chip select signal output to the D-RAM
75
LVS4
—
Digital ground
76
DRBS
O
Bank select signal output to the D-RAM
77, 78
DRDQM0, DRDQM1
O
Mask control signal output to the D-RAM
79
IVS5
—
Ground
80
NC
—
Not used. (Open)
81
SYSRST
I
Reset signal input from the system controller “L”: reset
82
IRDIN
I
IR data input pin Not used. (Fixed at “L”)
83
NC
—
Not used. (Open)
84
VDD1
—
Digital power supply (+2.5 V)
85
V16M
—
Not used. (Open)
86
DOUT
O
Digital audio signal output Not used. (Open)
87
L CDLRCK
I
L/R sampling clock signal (44.1 kHz) input
88
LRCK
O
L/R sampling clock signal (44.1 kHz) output
89
VSS1
—
Digital ground
90
L CDDATA
I
Serial data input
91
PCMD
O
Serial data output
92
L CDBCK
I
Bit clock signal (2.8224 MHz) input
93
BCK
O
Bit clock signal (2.8224 MHz) output
94
EMPH
—
Not used. (Open)
95
L SQSO
I
Subcode-Q 80-bit, PCM peak and level data, CD text data input
96
SQSO
O
Subcode-Q 80-bit, PCM peak and level data, CD text data output
97
VDD2
—
Digital power supply (+2.5 V)
98
L SQCK
O
SQSO readout clock signal output
99
SQCK
I
SQSO readout clock signal input
100
SBSO
—
Not used. (Open)
101
EXCK
—
Not used. (Fixed at “L”.)
102
DATA
I
Serial data input
103
L DDAT
O
Serial data output
104
VSS2
—
Digital ground
105
L CDXRST
O
Reset signal output
106
XRST
I
Reset signal input
107
MUTE
I
Muting on/off control signal input. Not used. (Fixed at “L”.)
108
L XLAT
O
Serial data latch pulse signal output
109
XLAT
I
Serial data latch pulse signal input
110
L DCLK
O
Serial data transfer clock signal output
111
CLOK
I
Serial data transfer clock signal input
112
L SENS
I
SENS signal input
113
SENS
O
SENS signal output
114
L SLCK
O
SENS serial data readout clock signal output
115
SCLK
I
SENS serial data readout clock signal input
116
VDD3
—
Digital power supply (+2.5 V)
117
ATSK
—
Not used. (Fixed at “L”.)
118
XUGF
—
Not used. (Open)
119
XPCK
—
Not used. (Open)
120
L GFS
I
Guard frame sync signal input
121
GFS
O
Guard frame sync signal output
122
VSS3
—
Digital ground
123
L CDC2PO
I
C2 pointer signal input
124
C2PO
O
C2 pointer signal output
Pin No.
Pin Name
I/O
Pin Description
56
HCD-RV555
125
L SCOR
I
Subcode sync (S0+S1) detection signal input
126
SCOR
O
Subcode sync (S0+S1) detection signal output
127
COUT
—
Not used. (Open)
128
VDD4
—
Digital ground
129
MIRR
—
Not used. (Open)
130
DFCT
—
Not used. (Open)
131
L FOK
I/O
Focus OK signal input/output
132
FOK
I/O
Focus OK signal input/output
133
MDP
O
Spindle motor servo drive signal output
134
VSS4
—
Digital ground
135
SSTP
I
Detection signal input from limit in switch
The optical pick-up is inner position when “H”
136
FSTO
—
Not used. (Open)
137
SFDR
O
Sled motor servo drive signal (+) output
138
SRDR
O
Sled motor servo drive signal (–) output
139
VDD5
—
Digital power supply (+2.5 V)
140
TFDR
O
Tracking coil servo drive signal (+) output
141
TRDR
O
Tracking coil servo drive signal (–) output
142
FFDR
O
Focus coil servo drive signal (+) output
143
FRDR
O
Focus coil servo drive signal (–) output
144
VSS5
—
Digital ground
145
WFCK
—
Not used. (Open)
146
WDCK
—
Not used. (Open)
147
ASYE
—
Not used. (Fixed at “H”)
148
VDD6
—
Digital power supply (+2.5 V)
149
XTAI
I
Main system clock input (33.8688 MHz)
150
XTAO
O
Main system clock output (33.8688 MHz)
151
VSS6
—
Digital ground
152
TES1
I
Input for the test Not used. (Fixed at “L”)
153
TEST
I
Input for the test Not used. (Fixed at “L”)
154, 155
NC
—
Not used. (pin 154: Open, Pin 155: Fixed at “L”.)
156
AVD0
—
Analog power supply (+2.5 V)
157
IGEN
I
Operational amplifier constant current input
158
AVS0
—
Analog ground
159
ADIO
—
Not used. (Open)
160
RFDC
I
RF signal input from the RF amplifier
161
CE
I
Center servo analog signal input
162
TE
I
Tracking error signal input
163
SE
I
Sled error signal input
164
FE
I
Focus error signal input
165
VC
I
Center voltage (+1.65 V) input
166
VPCO
O
Wide-band EFM PLL charge pump output
167
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
168
FILO
O
Master PLL filter output
169
FILI
I
Master PLL filter input
170
PCO
O
Master PLL charge pump output
171
CLTV
I
Multiplier VCO1 control voltage input
172
AVS1
—
Analog ground
173
RFAC
I
EFM signal input from the RF amplifier
174
BIAS
I
Asymmetry circuit constant current input
Pin No.
Pin Name
I/O
Pin Description
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