Sony HCD-RV22 / HCD-RV55 / MHC-RV22 / MHC-RV55 Service Manual ▷ View online
53
HCD-RV22/RV55
Pin No.
Pin Name
I/O
Pin Description
67
IVS4
—
Ground pin (for I/O)
68
DRCAS
O
Column address strobe signal output to the D-RAM
69
LVD4
—
Digital power supply pin (+2.5 V) (for AV decoder block)
70
DRCK
O
Clock signal output to the D-RAM
71
IVD5
—
Power supply pin (+3.3 V) (for I/O)
72
DRRAS
O
Row address strobe signal output to the D-RAM
73
DRWEL
O
Write enable signal output to the D-RAM
74
NVOEL
O
Chip select signal output to the D-RAM
75
LVS4
—
Digital ground pin (for AV decoder block)
76
DRBS
O
Bank select signal output to the D-RAM
77, 78
DRDQM0, DRDQM1
O
Mask control signal output to the D-RAM
79
IVS5
—
Ground pin (for I/O)
80
NC
—
Not used. (Open)
81
SYSRST
I
Reset signal input from the system controller “L”: reset
82
IRDIN
I
IR data input pin Not used. (Open)
83
NC
—
Not used. (Open)
84
VDD1
—
Digital power supply pin (+2.5 V) (for CD-DSP block)
85
V16M
O
Wide-band EFM PLL VCO2 oscillation output Not used. (Open)
86
DOUT
O
Digital audio signal output Not used. (Open)
87
L CDLRCK
I
L/R sampling clock signal (44.1 kHz) input
88
LRCK
O
L/R sampling clock signal (44.1 kHz) output
89
VSS1
—
Digital ground pin
90
L CDDATA
I
Serial data input
91
PCMD
O
Serial data output
92
L CDBCK
I
Bit clock signal (2.8224 MHz) input
93
BCK
O
Bit clock signal (2.8224 MHz) output
94
EMPH
O
“L” is output when playback disc is emphasis off
“H” is output when playback disc is emphasis on Not used. (Open)
95
L SQSO
I
Subcode-Q 80-bit, PCM peak and level data, CD text data input
96
SQSO
O
Subcode-Q 80-bit, PCM peak and level data, CD text data output
97
VDD2
—
Digital power supply pin (+2.5 V) (for CD-DSP block)
98
L SQCK
O
SQSO readout clock signal output
99
SQCK
I
SQSO readout clock signal input
100
SBSO
O
Subcode P to W serial data ooutput Not used. (Open)
101
EXCK
I
SBSO readout clock signal input Not used. (Fixed at “L”.)
102
DATA
I
Serial data input
103
L DDAT
O
Serial data output
104
VSS2
—
Digital ground pin
105
L CDXRST
O
Reset signal output “L”: reset
106
XRST
I
Reset signal input “L”: reset
107
MUTE
I
Muting on/off control signal input. “H”: muting on Not used. (Fixed at “L”.)
108
L XLAT
O
Serial data latch pulse signal output
109
XLAT
I
Serial data latch pulse signal input
110
L DCLK
O
Serial data transfer clock signal output
111
CLOK
I
Serial data transfer clock signal input
54
HCD-RV22/RV55
Pin No.
Pin Name
I/O
Pin Description
112
L SENS
I
SENS signal input
113
SENS
O
SENS signal output
114
L SLCK
O
SENS serial data readout clock signal output
115
SCLK
I
SENS serial data readout clock signal input
116
VDD3
—
Digital power supply pin (+2.5 V) (for CD-DSP block)
117
ATSK
I/O
Input/output for anti-shock Not used. (Fixed at “L”.)
118
XUGF
O
XUGF signal output Not used. (Open)
119
XPCK
O
XPCK signal output Not used. (Open)
120
L GFS
I
Guard frame sync signal input
121
GFS
O
Guard frame sync signal output
122
VSS3
—
Digital ground pin
123
L CDC2PO
I
C2 pointer signal input
124
C2PO
O
C2 pointer signal output
125
L SCOR
I
Subcode sync (S0+S1) detection signal input
126
SCOR
O
Subcode sync (S0+S1) detection signal output
127
COUT
O
Numbers of track counted signal output Not used. (Open)
128
VDD4
—
Digital ground pin (for CD-DSP block)
129
MIRR
I/O
Mirror signal input/output Not used. (Open)
130
DFCT
I/O
Defect signal input/output Not used. (Open)
131
L FOK
I/O
Focus OK signal input/output
132
FOK
I/O
Focus OK signal input/output
133
MDP
O
Spindle motor servo drive signal output
134
VSS4
—
Digital ground pin
135
SSTP
I
Detection signal input from limit in swich
The optical pick-up is inner position when “H”
136
FSTO
O
2/3 frequency-division output of the XTAI (pin 149) Not used. (Open)
137
SFDR
O
Sled motor servo drive signal (+) output
138
SRDR
O
Sled motor servo drive signal (–) output
139
VDD5
—
Digital power supply pin (+2.5 V) (for CD-DSP block)
140
TFDR
O
Tracking coil servo drive signal (+) output
141
TRDR
O
Tracking coil servo drive signal (–) output
142
FFDR
O
Focus coil servo drive signal (+) output
143
FRDR
O
Focus coil servo drive signal (–) output
144
VSS5
—
Digital ground pin
145
WFCK
O
Write frame clock signal output Not used. (Open)
146
WDCK
O
Word clock signal output Not used. (Open)
147
ASYE
I
Asymmetry circuit on/off control signal input “L”: off, “H”: on Not used. (Open)
148
VDD6
—
Digital power supply pin (+2.5 V) (for CD-DSP block)
149
XTAI
I
Main system clock input (33.8688 MHz)
150
XTAO
O
Main system clock output (33.8688 MHz)
151
VSS6
—
Digital ground pin
152
TES1
I
Input for the test Normally: fixed at “L”.
153
TEST
I
Input for the test Normally: fixed at “L”.
154, 155
NC
—
Not used. (pin 154: Open, Pin 155: Fixed at “L”.)
156
AVD0
—
Analog power supply pin (+2.5 V)
157
IGEN
I
Operational amplifier constant current input
55
HCD-RV22/RV55
Pin No.
Pin Name
I/O
Pin Description
158
AVS0
—
Analog ground pin
159
ADIO
O
Output for the test Not used.
160
RFDC
I
RF signal input from the RF amplifier
161
CE
I
Center servo analog signal input
162
TE
I
Tracking error signal input from the RF amplifier
163
SE
I
Sled error signal input from the RF amplifier
164
FE
I
Focus error signal input from the RF amplifier
165
VC
I
Center voltage (+1.65 V) input
166
VPCO
O
Wide-band EFM PLL charge pump output
167
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
168
FILO
O
Master PLL filter output
169
FILI
I
Master PLL filter input
170
PCO
O
Master PLL charge pump output
171
CLTV
I
Multiplier VCO1 control voltage input
172
AVS1
—
Analog ground pin
173
RFAC
I
EFM signal input from the RF amplifier
174
BIAS
I
Asymmetry circuit constant current input
175
ASYI
I
Asymmetry comparator voltage input
176
ASYO
O
EFM full-swing output
177
AVD1
—
Analog power supply pin (2.5 V)
178
VDD7
—
Digital power supply pin (+2.5 V) (for CD-DSP block)
179
SOUT
O
Serial data output Not used. (Open)
180
SOCK
O
Serial data readout clock signal output Not used. (Open)
181
XOLT
O
Serial data latch pulse signal output Not used. (Open)
182
C4M
O
4.2336 MHz clock signal output Not used. (Open)
183
LOCK
O
GFS is sampled by 460 Hz “H” output when GFS is “H”
184
VSS7
—
Digital ground pin
185
MD2
I
Digital out on/off control signal input “L”: digital out off, “H”: digital out on
Not used. (Fixed at “L”.)
186
SCSY
I
Guard subcode sync (S0+S1) resynchronization input Not used. (Fixed at “L”.)
187
PWMI
I
Spindle motor external control signal input Not used. (Fixed at “L”.)
188
VDD8
—
Digital power supply pin (+2.5 V) (for CD-DSP block )
189
XTSL
I
Input for the system clock frequency setting
“L”: 16.9344 MHz, “H”: 33.8688 MHz Fixed at “H” in this set
190
VSS8
—
Digital ground pin
191
PVS2
—
Analog ground pin (for PLL2)
192
LPFI
I
Connected of PLL2 filter
193
LPFO
O
Connected of PLL2 filter
194
PVD2
—
Analog power supply pin (+2.5 V) (for PLL2)
195, 196
NC
—
Not used. (Open)
197
PVD1
—
Analog power supply pin (+2.5 V) (for PLL1)
198
PVS1
—
Analog ground pin (for PLL1)
199
TMODE0
I
Selection signal input for the test Not used. (Fixed at “L”.)
200
AUDDTI
I
Serial audio data input Not used. (Fixd at “L”.)
201
AUDDTO0
O
Serial audio data output to the digital filter
56
HCD-RV22/RV55
Pin No.
Pin Name
I/O
Pin Description
202
AUDDTO1
O
Serial audio data output Not used. (Open)
203
AUDBCK
O
Serial audio bit clock signal (2.8224 MHz) output to the digital filter
204
AUDLRCK
O
Serial audio L/R sampling clock signal (44.1 kHz) output to the digital filter
205
AUDXCLKO
O
Serial audio clock signal output to the digital filter
206
CLKA
I
Sub system clock input (27 MHz)
207
CLKB
O
Sub system clock output (27 MHz)
208
VDD9
—
Digital power supply pin (+2.5 V) (for CD-DSP block)
209
THRCLK
I
Clock signal input for the test Not used. (Open)
210
TESTEN
I
Setting pin for the test Normally : fixed at “L”
211
TCLK
I
Clock signal input for the test Not used. (Fixd at “L”)
212
TMODE1
I
Selection signal input for the test Not used. (Fixd at “L”)
213
TRST
I
Reset signal input for the test Not sused. (Open)
214
VSS9
—
Digital ground pin
215
NC
—
Not used. (Fixd at “L”.)
216
V AVD1
—
Analog power supply pin (+2.5 V) (for D/A converter)
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