Sony HCD-MX500I / HCD-MX550I Service Manual ▷ View online
HCD-MX500i/MX550i
49
• IC Pin Function Description
BD96 BOARD IC101 TC94A70FG-101 (CD-MP3 PROCESSOR) (US and Canadian models)
BD96U BOARD IC101 TC94A70FG-101 (CD-MP3 PROCESSOR) (Except US and Canadian models)
BD96U BOARD IC101 TC94A70FG-101 (CD-MP3 PROCESSOR) (Except US and Canadian models)
Pin No.
Pin Name
I/O
Description
1
AVSS3
-
Ground terminal
2
RFZI
I
RF ripple zero crossing signal input terminal
3
RFRP
O
RF ripple signal output terminal
4
SBAD
O
Sub beam addition signal output terminal Not used
5
FEO
O
Focus error signal output terminal Not used
6
TEO
O
Tracking error signal output terminal
7
TEZI
I
Tracking error zero crossing signal input terminal
8
AVDD3
-
Power supply terminal (+3.3V)
9
FOO
O
Focus coil drive signal output terminal
10
TRO
O
Tracking coil drive signal output terminal
11
VREF
I
Reference voltage (+1.65V) input terminal
12
FMO
O
Sled motor drive signal output terminal
13
DMO
O
Spindle motor drive signal output terminal
14
VSSP3
-
Ground terminal
15
VCOI
I
VCO control voltage input terminal
16
VDDP3
-
Power supply terminal (+3.3V)
17
VDD1
-
Power supply terminal (+1.5V)
18
VSS1
-
Ground terminal
19
FGIN
I
FG signal input terminal Not used
20
IN_SW
I
Disc inner position detection signal input terminal
21
/DFCT
O
Not used
22
XVSS3
-
Ground terminal
23
XI
I
System clock input terminal (16.934 MHz)
24
XO
O
System clock output terminal (16.934 MHz)
25
XVDD3
-
Power supply terminal (+3.3V)
26
DVSS3
-
Ground terminal
27
ROUT
O
Audio data (R-ch) output to the input selector
28
DVDD3
-
Power supply terminal (+3.3V)
29
DVR
O
Reference voltage (+1.65V) output terminal
30
LOUT
O
Audio data (L-ch) output to the input selector
31
DVSS3
-
Ground terminal
32
VDDT3
-
Power supply terminal (+3.3V)
33
VSS1
-
Ground terminal
34
VDD1
-
Power supply terminal (+1.5V)
35
VDDM1
-
Power supply terminal (+1.5V)
36
SRAMSTB
I
S-RAM standby mode control signal input terminal Fixed at “L” in this set
37
XRST
I
Reset signal input from the system controller “L”: reset
38 to 41
BUS0 to BUS3
I
Serial data input from the system controller (US and Canadian models)
Serial data input from the system controller and USB controller
(Except US and Canadian models)
Serial data input from the system controller and USB controller
(Except US and Canadian models)
42
BUCK
I
Serial data transfer clock signal input from the system controller
43
XCCE
I
Chip enable signal input from the system controller
44
TEST
I
Setting terminal for test mode Normally fi xed at “L”
45
IRQ
I
Interrupt request signal input terminal Not used
46
ST_REQ/CKO
O
Request signal output terminal Not used
47
AOUT2
O
Audio data output terminal (Except US and Canadian models only)
48
REQ
O
Request signal output to the system controller (US and Canadian models)
Request signal output to the system controller and USB controller
(Except US and Canadian models)
Request signal output to the system controller and USB controller
(Except US and Canadian models)
49
PIO1/ST_REQ
O
Request signal output to the USB controller (Except US and Canadian models only)
50
PIO2
O
Not used
51
GATE
I
Gate signal input terminal (Except US and Canadian models only)
52
VSS1
-
Ground terminal
53
VDDT3
-
Power supply terminal (+3.3V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
FOK
O
Not used
Ver. 1.1
HCD-MX500i/MX550i
50
Pin No.
Pin Name
I/O
Description
56
IPF
O
Not used
57
/LOCK
O
Not used
58
ZDET
O
Zero detection signal output terminal Not used
59
GPIN
I
Not used
60
MS
I
Micro controller interface mode selection signal input terminal Fixed at “H” in this set
61
DOUT
O
Digital audio data output terminal Not used
62
AOUT1
O
Audio data output terminal Not used
63
BCKO
O
Bit clock signal output terminal (Except US and Canadian models only)
64
LRCKO
O
L/R sampling clock signal output terminal Not used
65
AIN
I
Digital audio data input terminal (Except US and Canadian models only)
66
BCKI
I
Bit clock signal input terminal (Except US and Canadian models only)
67
LRCKI
I
L/R sampling clock signal input terminal (Except US and Canadian models only)
68
VDD1
-
Power supply terminal (+1.5V)
69
VSS1
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
76
LPFO
O
Signal output from the operation amplifi er for PLL loop fi lter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO fi lter output terminal
79
PVSS3
-
Ground terminal
80
SLCO
O
EFM slice level output terminal
81
RFI
I
RF signal input terminal
82
RFRPI
I
RF ripple signal input terminal
83
RFEQ0
O
EFM slice level output terminal
84
VRO
O
Reference voltage (+1.65V) output terminal
85
RESIN
O
External resistor connection terminal
86
VMDIR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass fi lter terminal for RFEQO offset correction
88
AGCI
I
RF signal amplitude adjustment amplifi cation input terminal
89
RFO
O
RF signal generation amplifi cation output terminal
90
RVDD3
-
Power supply terminal (+3.3V)
91
LDO
O
Laser diode on/off control signal output to the automatic power control circuit
“H”: laser diode on
“H”: laser diode on
92
MDI
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
-
Ground terminal
94
C
I
Main beam (D) input from the optical pick-up block
95
A
I
Main beam (B) input from the optical pick-up block
96
D
I
Main beam (C) input from the optical pick-up block
97
B
I
Main beam (A) input from the optical pick-up block
98
F
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection terminal
100
E
I
Sub beam (E) input from the optical pick-up block
Ver. 1.1
HCD-MX500i/MX550i
51
BD96U BOARD IC401 92CD28AFG-7FU8 (M (USB CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
USB-RST
I
Reset signal input from the system controller “L”: reset
2
I-USB-DI
I
Ready to send signal input from the system controller
3, 4
INT1, INT2
O
Not used
5
INT3
I
Function selection signal input terminal Fixed at “H” in this set
6
DVCC3B
-
Power supply terminal (+3.3V)
7 to 9
XT1, XT2, PWE
-
Not used
10
DVSS1B
-
Ground terminal
11
DVCC1B
-
Power supply terminal Not used
12
RVOUT1
O
Reference voltage (+3.3V) output terminal Not used
13, 14
RVIN
I
Reference voltage (+3.3V) input terminal
15
RVOUT2
O
Reference voltage (+3.3V) output terminal Not used
16
DVCC1A
-
Power supply terminal Not used
17
DVSS1A
-
Ground terminal
18 to 25
D0 to D7
I/O
Two-way data bus with the S-RAM
26
DVSS
-
Ground terminal
27
DVCC3A
-
Power supply terminal (+3.3V)
28 to 35
D8 to D15
I/O
Two-way data bus with the S-RAM
36
A0
O
Address signal output terminal Not used
37 to 43
A1 to A7
O
Address signal output to the S-RAM
44
DVSS
-
Ground terminal
45
DVCC3A
-
Power supply terminal (+3.3V)
46 to 54
A8 to A16
O
Address signal output to the S-RAM
55 to 58
BUS0-U to BUS3-U
O
Serial data output to the CD-MP3 processor
59
BUCK-U
O
Serial data transfer clock signal output to the CD-MP3 processor
60
CCE-U
O
Chip enable signal output to the CD-MP3 processor
61
A23
O
Not used
62
DVSS
-
Ground terminal
63
DVCC3A
-
Power supply terminal (+3.3V)
64
RD
O
Output enable signal output to the S-RAM
65
SRWR
O
Write enable signal output to the S-RAM
66
SRLLB
O
Lower-byte control signal output to the S-RAM
67
SRLUB
O
Upper-byte control signal output to the S-RAM
68
TA0IN
O
Not used
69
BOOT
I
Boot mode selection signal input terminal “L”: boot mode
70
SRAM-CS
O
Chip select signal output to the S-RAM
71
LRCK
O
L/R sampling clock signal output to the CD-MP3 processor
72
AM1
I
Function mode selection signal input terminal Fixed at “H” in this set
73
X2
O
System clock output terminal (9 MHz)
74
DVSS
-
Ground terminal
75
X1
I
System clock input terminal (9 MHz)
76
DVCC3A
-
Power supply terminal (+3.3V)
77
USBOC
I
Over current detection signal input terminal
78
USBPON
O
USB VBUS power on/off control signal output terminal “H”: power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D-
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input terminal Fixed at “H” in this set
82
X1USB
O
Not used
83
DVSS
-
Ground terminal
84
O-USB-DO
O
Clear to send signal output to the system controller
85
DATA
I
Audio data input from the CD-MP3 processor
86
CLK
I
Audio data transfer clock signal input from CD-MP3 processor
87
O-USB-SO
O
Serial data output to the system controller
88
I-USB-SI
I
Serial data input from the system controller
89
SPCLK
-
Not used
90
SO0
-
Not used
91
SI0
-
Not used
92
BCK
O
Bit clock signal output to the CD-MP3 processor
93
A-IN
O
Audio data output to the CD-MP3 processor
HCD-MX500i/MX550i
52
Pin No.
Pin Name
I/O
Description
94
GATE
O
Gate signal output to the CD-MP3 processor
95
DVCC3A
-
Power supply terminal (+3.3V)
96
REQ-U
I
Request signal input from the CD-MP3 processor
97
ST-REQ
I
Request signal input from the CD-MP3 processor
98, 99
PG1, PG0
I
Function selection signal input terminal Fixed at “H” in this set
100
DVSS
-
Ground terminal
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