Sony HCD-MJ1 / HCD-MJ1A Service Manual ▷ View online
– 25 –
Pin No.
Pin name
I/O
Description
80
AMUTE
O
Line out muting signal output.
81
LDOUT
O
Loading motor (M191) control output. *1
82
LDIN
O
Loading motor (M191) control output. *1
83
CHKIN
I
Detection signal input from the chucking in switch (S193). When chucking : “L”
84
INSW
I
Detection signal input from the loading in switch (S192).
“L” at the position where the head descends, Others : “H”
85
OUTSW
I
Detection signal input from the loading out switch (S191).
“L” at the position of load out, Others : “H”
86
PROTECT
I
Rec proof detection signal input from the protect detector switch (S102-1).
When protect : “H”
87
REFLECT
I
Disc reflection rate detection signal input from the reflect detector switch (S102-2).
“H” : Low reflection rate disc
88
LIMIT IN
I
Detection signal input from the limit in switch (S101).
When sled limit in : “L”
89
232C. 4
O
UART data transmission request signal output to mPD78052G (IC301)
90
232C. 3
I
UART data transmission reqeust signal input from mPD78052G (IC301)
91
232C. 2
I
UART data input from mPD78052GC (IC301)
92
232C. 1
O
UART data output to mPD78052GC (IC301)
93–96
O
Not used (Fixed at “L”).
97
AVSS (AGND)
–
Ground terminal.
98
VREF (+5V)
I
Reference voltage input (+5V)
Timer record /time playback/time OFF selection signal input terminal.
99
TIMER REC/PLAY
I
When timer recording : “H”, When timer playback : “L”,
When timer OFF : Center point voltage (+2.5V)
Not used this set (Fixed at “L”)
100
INPUT SELECT
I
Analog/digital in selection signal input terminal
When analog in : “L”, When digital in : “H” Not used this set (Fixed at “L”)
*
1 Loading motor control
Mode
IN
OUT
BRAKE
Terminal
LDIN pin
*™
“H”
“L”
“H”
LDOUT pin
*¡
“L”
“H”
“H”
– 26 –
Pin No.
Pin name
I/O
Description
1
VDD
–
Power supply terminal. (+5V)
2
SWDT
I
Write data signal input from the system controller (IC201).
3
SCK
I
Serial clock signal input from the system controller (IC201).
4
XLAT
I
Serial latch signal input from the system controller (IC201).
5
SRDT
O
Read data signal output to the system controller (IC201).
6
SENSE
O
Internal status (SENSE) output to the system controller (IC201).
7
SCMD0
I
Serial command control mode input from the system controller. (Fixed at “H”)
8
SCMD1
I
Serial command control mode input from the system controller. (Fixed at “H”)
9
XINT
O
Interruption status output to the system controller (IC201).
10
RCPB
I
Record/playback selection signal input. Not used this set. (Fixed at “L”)
11
WRMN
I
Write/monitor mode selection signal input from the system controller (IC201).
12
TX
–
Writing data transmission timing input from the system controller (IC201).
Used together with the magnetic field head ON/OFF output.
13
VSS
–
Ground terminal.
14
SICK
I
Chip reserve terminal. (Fixed at “L”)
15
IDSL
I
Chip reserve terminal. (Fixed at “L”)
16
XILT
I
Chip reserve terminal. (Fixed at “H”)
17
XRST
I
Reset signal input from the system controller (IC201).
When reset : “L”
18–21
TS0–TS3
I
Test input terminal. (Fixed at “L”)
22
EXIR
I
Chip reserve terminal. (Fixed at “L”)
23
SASL
I
Single use the block selection. “L” : ATRAC, “H” : RAM Controller (Fixed at “L”)
24
SNGLE
I
Normally fixed at “L”, Fixed at “H” when the ATRAC or RAM controller is single used.
(Fixed at “L”)
25
VSS
–
Ground terminal.
26
AIRCPB
O
Record/playback mode signal output terminal of the ATRAC or external audio block.
Not
used this set.
27
XRQ
I/O
XRQ signal input/output terminal of the ATRAC interface. Not used this set.
28
ADTO
I/O
Decoder data signal input/output terminal of the ATRAC. Not used this set.
29
ADTI
I/O
Encoder data signal input/output terminal of the ATRAC. Not used this set.
30
XALT
I/O
XALT signal input/output terminal of the ATRAC interface. Not used this set.
31
ACK
I/O
ACK signal input/output terminal of the ATRAC interface. Not used this set.
32
AC2
I/O
Error data signal input/output terminal of the ATRAC interface. Not used this set.
33
LCHST
I/O
Lch Start data signal input/output terminal of the ATRAC interface. Not used this set.
34
EXE
I/O
EXE signal input/output terminal of the ATRAC interface. Not used this set.
35
MUTE
I/O
MUTE signal input/output terminal of the ATRAC interface. Not used this set.
36
OSCO
O
45MHz clock oscillation output. (45MHz)
37
OSCI
I
45MHz clock oscillation input. (45MHz)
38
VSS
–
Ground terminal.
39
ATT
I/O
ATT signal input/output terminal of the ATRAC interface. Not used this set.
40
F86
O
11.6msec timing signal output terminal of the ATRAC block. Not used this set.
41
DOUT
O
Monitor/audio decode data signal output to the D/A converter (IC281).
42
ADIN
I
Recoding data signal input from the D/A converter (IC261).
43
ABCK
O
Bit clock signal output to the A/D, D/A converter (IC261, 281).
44
ALRCK
O
L/R clock signal output to the A/D, D/A converter (IC261, 281).
45-47
SA2-SA0
O
Address signal output. Not used this set (OPEN)
48,49
A11,A10
O
Address signal output. Not used this set
IC271 SHCCK PROOF MEMORY CONTROLLER, ATRAC ENCODER/DECODER (CXD2536R)
– 27 –
Pin No.
Pin name
I/O
Description
50
VSS
–
Ground terminal.
51
VDD
–
Power supply terminal. (+5V)
52– 55
A03– A00
O
Address signal output to the RAM (IC222)
56– 60
A04– A08
O
Address signal output to the RAM (IC222)
61
XOE
O
Output enable control signal output to the RAM (IC222).
62
XCAS
O
Column address strobe signal output to the RAM (IC222).
63
VSS
–
Ground terminal.
64
XCS
O
Chip select signal output. Not used this set
65
A09
O
Address signal output to the RAM (IC222).
66
XRAS
O
Row address strobe signal output to the RAM (IC222).
67
XWE
O
Write enable control signal output to the RAM (IC222).
68,69
D1, D0
I/O
RAM (IC222) data bus.
70,71
D2,D3
I/O
RAM (IC222) data bus.
72–74
D4–D6
I/O
Data bus. Not used this set (OPEN)
75
VSS
–
Ground terminal.
76
D7
I/O
Data bus. Not used this set (OPEN)
77
ERR
I/O
Input/output terminal of the error (C2PO) data signal to the external RAM.
Not used this set (OPEN)
78
EXTC2R
I
External RAM selection signal input for the error data writing.
(When “H” : External RAM) (Fixed at “L”).
79
BUSY
O
BUSY signal output of the RAM access. Not used this set (OPEN)
80
EMP
O
Empty or before the full of the ATRAC data. (When DSC=ASC+1 : “H” ). Not used this set.
81
FUL
O
Full or before the empty of the ATRAC data. (When ASC=DSC+1 : “H” ). Not used this set.
82
EQL
O
Empty of the ATRACK data. (when DSC=ASC : “H” ). Not used this set.
83
MDLK
O
Indicate the main/sub of the recording or playback data.
(When sub and linking : “H” , When the main : “L”). Not used this set.
84
CPSY
O
Interpolation sync signal output. Not used this set.
85
CTMD0
O
DSC counter mode output. Not used this set.
86
CTMD1
O
DSC counter mode output. Not used this set.
87
SPO
O
System clock (512Fs=22.5792MHz) signal output to CXD2535BR (IC121).
88
VSS
–
Ground terminal.
89
MDSY
O
Sync detection signal output of the main data. Not used this set.
90
LRCK
I
L/R clock (44.1kHz) signal input from CXD2535BR (IC121).
91
BCK
I
Bit clock (2.8224MHz) signal input from CXD2535BR (IC121).
C2PO (indicate the error mode of the data) signal input from CXD2535BR (IC121).
92
C2PO
I
When playback : C2PO (“H”), When digital recording : D. IN-Vflag,
When analog recording : “L”
When recording : Record audio data signal output to CXD2535BR (IC121).
93
DATA
I/O
When playback : playback audio data signal input from CXD2535BR (IC121).
94
DIDT
I
16-bit data input terminal for the digital audio in from the CXD2535BR(IC121).
95
DODT
O
16-bit data output terminal for the digital audio out from the CXD2535BR (IC121).
96
DIRCPB
O
Disc drive, Record or playback mode output of the EFM encoder/decoder.
Not used this set (Open)
97
MIN
I
Defect ON/OFF selection signal input from CXD2535BR (IC121).
98
SPOSL
I
IN/OUT selection input terminal of the pin *¶. ( “L” : IN, “H” : OUT) (Fixed at “H”)
99
MCKT1
O
Internal master clock signal output terminal of the RAM controller. Not used ths set.
100
VSS
–
Ground terminal.
– 28 –
Pin No.
Pin name
I/O
Description
1
LID SW
I
LID switch input (OPEN, CLOSE, SHUT switch).
2
MD RESET
I
Reset input for MD.
3
I
CADY sensor input terminal.
4
AVSS
–
Ground.
5
LID-OPEN
O
LID motor control output (open direction).
6
LID CLS
O
LID motor control output (close direction).
7
–
Not used.
8
DATA IN
I
Serial data input from MD.
9
DATA OUT
O
Serial data output to MD.
10
CTS
I
Clock input from 8 , 9 pin.
11
RTS
O
Clock output to 8 , 9 pin.
12
SDATA
O
Serial data output to FL driver.
13
SCK
O
Clock output to FL driver.
–––––
14
CS
O
Chip selector output to FL driver.
15
REST
O
Reset output to FL driver.
16
SUBQ
I
SUB “Q” input from CD.
17
OPEN
–
Not used.
18
SQCLK
O
SUB “Q” clock output to CD.
19
CCLOK
O
Master clock output to CD.
20
DATA
O
Data output to CD.
21
XLT
O
Latch output to CD.
22
DFLATCH
O
Latch output to CD digital filter.
23
FCSSW
O
output to Focus SW.
24
A MUTE
–
Not used.
25
BDRST
O
Reset output to CD.
––––––––––––––––––––
26
CD POWER
O
CD Block Power ON/OFF. ( “H” : ACT )
27
SENS
I
Sens input from CD.
28
ADJ
I
Terminal for test mode. ( “L” : Test mode )
29
IN SW
I
LOAD IN Switch input. ( close )
30
OUT SW
I
LOAD OUT Switch input. ( open )
31
LOD IN
O
Loading Motor drive output. ( open direction )
32
LOD OUT
O
Loading Motor drive output. ( close direction )
33
VSS
–
Ground.
34
–
Not used. ( open )
35
–
Not used. ( open )
––––––––––––––––––––––
36
SYS POWER
O
System power ON / OFF control. ( “L” : power ON )
37
–
Not used.
––––––––––––––––––––
38
ST POWER
O
ST Power ON / OFF control. ( “L” : ST ON )
––––––––––
39
TAPE
–
Not used.
40
–
Not used.
41
–
Not used.
42
STEREO
I
Stereo Signal input from ST block.
43
TUNED
I
Tuned Signal input from ST block.
44
DATA IN
I
Serial data input from ST block.
45
DATA OUT
O
Serial data output to ST block.
46
CLOCK
I/O
Clock input / output of the ST block.
IC301 MASTER CONTROL (
µ
PD78058GC-243-3B9)
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