Sony HCD-MG110 / HCD-MG310AV / MHC-MG110 / MHC-MG310AV Service Manual ▷ View online
HCD-MG110/MG310AV
46
46
POWER BOARD
(AC IN)
WHT
BLK
2
1
T902
POWER
TRANSFORMER
(SUB)
(CHASSIS)
N
MAIN BOARD
CN903
R
MAIN AMP
BOARD
CN502
(MG110)
1-680-803-
21
(21)
T901
POWER TRANSFORMER
(MAIN)
*
NOT REPLACEABLE:
BUILT IN TRANSFORMER
E
P
MAIN AMP BOARD
CN502
FUSE BOARD
1-682-126-
(MG310AV)
B
C
D
E
F
A
1
2
3
4
5
6
7
8
11
(11)
21
(21)
(AUS)
(US, CND, MX)
12
(12)
(MG110)
(MG310AV)
(US, CND, MX)
7-24. PRINTED WIRING BOARDS – POWER Section –
•
See page 26 for Circuit Boards Location.
• Semiconductor
Location
Ref. No.
Location
D901
C-2
D902
C-2
D911
E-2
D912
E-2
D913
E-2
D914
E-2
Q901
F-2
(Page 38)
(Page 40)
(Page 40)
Ver 1.3
HCD-MG110/MG310AV
47
47
(US, CND, MX)
(US, CND, MX)
(US, CND, MX)
7-25. SCHEMATIC DIAGRAM – POWER Section –
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : FM
no mark : FM
(Page 41)
(Page 41)
(Page 35)
The components identified by mark
0
or dotted
line with mark
0
are critical for safety.
Replace only with part number specified.
Les composants identifiés par une marque
0
sont
critiques pour la sécurité.
Ne les remplacer que
par une pièce portant le numéro spécifié.
Ver 1.3
HCD-MG110/MG310AV
48
48
7-26.
IC PIN FUNCTION DESCRIPTION
•
Pin No.
Pin Name
I/O
Description
1
SQSO
O
Subcode Q data output to the system controller (IC801)
2
SQCK
I
Subcode Q data reading clock signal input from the system controller (IC801)
3
XRST
I
System reset signal input from the system controller (IC801) “L”: reset
4
SYSM
I
Analog line muting on/off control signal input terminal “H”: line muting on
Not used (fixed at “L”)
Not used (fixed at “L”)
5
DATA
I
Command serial data input from the system controller (IC801)
6
XLAT
I
Command latch pulse input from the system controller (IC801)
7
CLOK
I
Command serial data transfer clock signal input from the system controller (IC801)
8
SENS
O
Internal status monitor output to the system controller (IC801)
9
SCLK
I
SENSE serial data reading clock input from the system controller (IC801)
10
VDD
—
Power supply terminal (+5V) (digital system)
11
ATSK
I/O
Input pin for anti-shock Not used (fixed at “L”)
12
SPOA
I
Microcomputer escape interface input A terminal Not used (fixed at “L”)
13
SPOB
I
Microcomputer escape interface input B terminal Not used (fixed at “L”)
14
XLON
O
Microcomputer escape interface output terminal Not used (open)
15
WFCK
O
WFCK output terminal Not used (open)
16
XUGF
O
Not used (open)
17
XPCK
O
Not used (open)
18
GFS
O
Not used (open)
19
C2PO
O
Not used (open)
20
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller (IC801)
21
COUT
I/O
Numbers of track counted signal input/output terminal Not used (open)
22
MIRR
I/O
Mirror signal input/output terminal Not used (open)
23
DFCT
I/O
Defect signal input/output terminal Not used (open)
24
FOK
I/O
Focus OK input/output terminal Not used (open)
25
LOCK
I/O
GFS is sampled by 460 Hz “H” when GFS is “H” Not used (open)
26
MDP
O
Spindle motor (M101) servo drive signal output to the BA5974FP (IC102)
27
SSTP
I
Limit in detect switch (S101) input terminal
28
SFDR
O
Sled servo drive PWM signal (+) output to the BA5974FP (IC102)
29
SRDR
O
Sled servo drive PWM signal (–) output to the BA5974FP (IC102)
30
TFDR
O
Tracking servo drive PWM signal (+) output to the BA5974FP (IC102)
31
TRDR
O
Tracking servo drive PWM signal (–) output to the BA5974FP (IC102)
32
FFDR
O
Focus servo drive PWM signal (+) output to the BA5974FP (IC102)
33
FRDR
O
Focus servo drive PWM signal (–) output to the BA5974FP (IC102)
34
VSS
—
Ground terminal (digital system)
35
TEST
I
Input terminal for the test (fixed at “L”)
36
TES1
I
Input terminal for the test (fixed at “L”)
37
XTSL
I
Input terminal for the system clock frequency setting “L”: 45.1584 MHz, “H”: 22.5792 MHz
(fixed at “L” in this set)
(fixed at “L” in this set)
38
VC
I
Middle point voltage (+2.5V) input from the CXA2581N (IC103)
39
FE
I
Focus error signal input from the CXA2581N (IC103)
40
SE
I
Sled error signal input from the CXA2581N (IC103)
41
TE
I
Tracking error signal input from the CXA2581N (IC103)
42
CE
I
Command chip enable signal input from the CXA2581N (IC103)
CD BOARD IC101 CXD3017Q
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
(DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, DIGITAL FILTER, D/A CONVERTER)
Pin No.
Pin Name
I/O
Description
43
RFDC
I
RF signal input from the CXA2581N (IC103)
44
ADIO
O
Monitor output of the A/D converter input signal Not used (open)
45
AVSS0
—
Ground terminal (digital system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
—
Power supply terminal (+5V) (digital system)
48
ASYO
O
Playback EFM full-swing output terminal
49
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
50
BIAS
I
Playback EFM asymmetry circuit constant current input terminal
51
RFAC
I
EFM signal input from the CXA2581N (IC103)
52
AVSS3
—
Ground terminal (digital system)
53
CLTV
I
Internal VCO control voltage input of the playback master PLL
54
FILO
O
Filter output for master clock of the playback master PLL
55
FILI
I
Filter input for master clock of the playback master PLL
56
PCO
O
Phase comparison output for master clock of the playback EFM master PLL
57
AVDD3
—
Power supply terminal (+5V) (digital system)
58
VSS
—
Ground terminal (digital system)
59
VDD
—
Power supply terminal (+5V) (digital system)
60
DOUT
O
Digital audio signal output to the DIGITAL OUT (CD) (IC361)
61
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal Not used (open)
62
PCMD
O
D/A interface serial data output terminal Not used (open)
63
BCK
O
Bit clock signal (2.8224 MHz) output terminal Not used (open)
64
EMPH
O
De-emphasis control signal output terminal Not used (open)
65
XVDD
—
Power supply terminal (+5V) (crystal oscillator system)
66
XTAI
I
System clock input terminal (16.9344 MHz)
67
XTAO
O
System clock output terminal (16.9344 MHz)
68
XVSS
—
Ground terminal (crystal oscillator system)
69
AVDD1
—
Power supply terminal (+5V) (analog system)
70
AOUT1
O
L-ch analog audio signal output terminal
71
AIN1
I
L-ch operational amplifiers input terminal
72
LOUT1
O
L-ch line output terminal
73
AVSS1
—
Ground terminal (analog system)
74
AVSS2
—
Ground terminal (analog system)
75
LOUT2
O
R-ch line output terminal
76
AIN2
I
R-ch operational amplifiers input terminal
77
AOUT2
O
R-ch analog audio signal output terminal
78
AVDD2
—
Power supply terminal (+5V) (analog system)
79
RMUT
O
R-ch line muting on/off control signal output terminal Not used (open)
80
LMUT
O
L-ch line muting on/off control signal output terminal Not used (open)
49
HCD-MG110/MG310AV
•
MAIN BOARD IC801 M30622MGA-A42FP (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
NC
—
Not used (open)
2
LOAD POS
O
Loading motor drive signal (load-out direction) output the motor driver (IC881)
3
LOAD NEG
O
Loading motor drive signal (load-in direction) output the motor driver (IC881)
4
RMC
I
Remote control signal input from the remote control receiver (IC702)
5
TABLE POS
O
Table motor drive signal (counterclockwise) output to the motor driver (IC881)
6
LOAD IN SW
I
Load in/out detect switch (S842) input “L”: load in
7
LOAD OUT SW
I
Load in/out detect switch (S842) input “L”: load out
8
—
—
Not used (fixed at “L”)
9
CNVSS
—
Not used
10
SUBXIN
I
Sub system clock input terminal (32.768 kHz)
11
SUBXOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input from the reset signal generator (IC802) “L”: reset
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+5V)
17
NC
—
Not used (fixed at “H”)
18
T-SENS2
I
Table position sensor (IC13) input terminal
19
SCOR
I
Subcode sync (S0+S1) detection signal input from the CXD3017Q (IC101)
20
KB-SCL
O
Serial data transfer clock signal output to the KEYBOARD (J801)
21
C-MUTE
O
Muting on/off control signal output terminal “H”: muting (center speaker) (MG310AV only)
22
PWM1
O
Focus servo drive PWM signal output to the CXA2581N (IC103)
23
R-MUTE
O
Muting on/off control signal output terminal “H”: muting (rear speakers) (MG310AV only)
24
PWM2
O
PWM signal output to the CXA2581N (IC103)
25
PL-RQ
O
Serial data latch pulse output to the M62464FP (IC401) (MG310AV only)
26
PWM3
O
RFDC PWM signal output to the CXA2581N (IC103)
27
PL-DATA
O
Serial data output to the M62464FP (IC401) (MG310AV only)
28
PL-CLK
O
Serial data transfer clock signal output to the M62464FP (IC401) (MG310AV only)
29
IIC CLK
I/O
Communication data reading clock signal input or transfer clock signal output with the display
controller (IC701)
controller (IC701)
30
IIC DATA
I/O
Communication data bus with the display controller (IC701)
31
NC
—
Not used
32
C-SQSO
I
Subcode Q data input from the CXD3017Q (IC101)
33
C-SQCK
O
Subcode Q data reading clock signal output to the CXD3017Q (IC101)
34
FRONT
O
Selection signal output of the rear speaker output signal to the BU4066BC (IC307)
“H”: Same the front channel (MG310AV only)
“H”: Same the front channel (MG310AV only)
35
REAR
O
Selection signal output of the rear speaker output signal to the BU4066BC (IC307)
“H”: Rear channel (MG310AV only)
“H”: Rear channel (MG310AV only)
36
KB-SDA
I
Keyboard data input from the KEYBOARD (J801)
37
KB-CTRL
O
Keyboard control signal output to the KEYBOARD (J801)
38
S/W MUTE
O
Muting on/off control signal output terminal “H”: muting (super woofer) (MG310AV only)
39
NC
—
Not used (open)
40
R-RELAY
O
Relay drive signal output for the surround speaker (rear and center) protection “H”: on
(MG310AV only)
(MG310AV only)
41
NC
—
Not used (fixed at “L”)
•
MAIN BOARD IC801 M30622MGA-A68FP (SYSTEM CONTROLLER)
Ver 1.1
Click on the first or last page to see other HCD-MG110 / HCD-MG310AV / MHC-MG110 / MHC-MG310AV service manuals if exist.