Sony HCD-M70 Service Manual ▷ View online
HCD-M70
32
32
THERMAL
SHUTDOWN
BIPOLAR
TRANSCONDACTANCE
INPUT STAGE
STANDBY/
MUTE
BOOST-
STRAP
MOS GAIN &
LEVEL SHIFTING
STAGE
STBY
-GND
IN–
IN+
IN+ MUTE
NC
BOOSTSTRAP
+VS
–VS
STBY
MUTE
NC
NC
+PWVS
OUT
–PWVS
14 15
12
13
10
11
8 9
6
7
5
3
4
1 2
+
–
MOS
OUTPUT
STAGE
SHORT
CIRCUIT
PROTECTION
APC PD AMP
APC LD AMP
RF SUMMING AMP
RF EQ AMP
FOCUS ERROR AMP
TRACKING
ERROR AMP
VC BUFFER
VCC
50µA
VEE
VEE
VC
VC
VC
VC
VC
VC
VC
VC
VC
VC
VCC
VEE
VCC
VEE
VEE
VC
VCC
LC/PD
LD ON
HOLD SW
AGC CONT
RFTC
RF I
RF O
RFE
TE
FE
RF BOT
HOLD
AGC VTH
LD
PD
A
B
C
D
VEE
F
E
VC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
+
–
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
+
–
–
VCC
+
–
–
+
–
–
+
–
–
+
–
+
–
–
+
–
–
+
–
–
+
–
–
+
–
LEVEL SHIFT
INTERFACE
INTERFACE
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
MUTE
THERMAL
SHUTDOWN
VREFOUT
VREFIN
POWVCC
CH1FIN
CH1RIN
CH2FIN
CH2RIN
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
CAP
A
IN1
CAP
A
IN2
GND
PRFVCC
MUTE
POWVCC
CH4SIN'
CH4SIN
CH4BIN
CH3FIN
CH3RIN
CH3OUTR
CH3OUTF
CH4OUTR
CH4OUTF
CAP
A
IN3
GND
• IC Block Diagrams
– CD Board –
– CD Board –
IC101
CXD2587Q
IC102
BA5974FP-E2
IC103
CXA2568M-T6
– MAIN Board –
IC101, 201
TDA7296
TE
RFDC
CE
IGEN
AVSS0
ADIO
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTOR
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
33
HCD-M70
GND
OUT1
VCTL
VZ1
VZ2
IN1
IN2
VCC1
VCC2
OUT2
5
6
7
8 9 10
1
2 3
4
DRIVER OUT
PRE DRIVER
LOGIC
SWITCH
TSD
BIAS
ANALOG
DIGIT
AL
RCLK
NC
XO
XI
VSS2
T2
VDD2
T1
QUAL
RDA
T
VREF
MUX
VDD1
VSS1
VSS3
CMP
1
4
3
6
5
8
7
2
14
15
16
13
12 11 10
9
CLOCK
PLL 57kHz
RDS/ARI
COMPARATOR
8th SWITCHED
CAPACITOR
FILTER
ANTI-ALIASING
FILTER
BIPHASE
DECODER
PLL
1187.5Hz
DEFFERENTIAL
DECODER
TEST
30
29
1
2
CCB
INTERFACE
CONTROL
CIRCUIT
LOGIC
CIRCUIT
CONTROL
CIRCUIT
26
+
–
25
24
+
–
23 22 21
20 19 18 17
+
–
+
–
–
5
+
–
–
6
7
+
–
–
8
9
10
11 12 13 14
+
–
–
+
–
3
LOUT
LBASS2
LBASS1
LTRE
LIN
LSELO
L4
L3
L2
L1
15
NC
VSS
4
TEST
VDD
ROUT
RBASS2
RBASS1
RTRE
RIN
RSELO
R4
R3
R2
R1
16
NC
CL
DI
CE
28
+
–
RVREF
+
–
LVREF
VREF
27
NC
– CONTROL Board –
IC320
KA3082
IC323
LC75342
IC326
BU1924F-E2 (AEP, UK)
34
HCD-M70
6-18.
IC PIN FUNCTION DESCRIPTION
•
MAIN BOARD IC801 CXP83124A-053Q (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
SENSOR
I
Tape end detect switch input terminal “H” input when the tape end detected
2
RDS-IN
I
Serial data transfer clock signal input from the RDS decoder
(RDS decoder is used for the AEP and UK models)
(RDS decoder is used for the AEP and UK models)
3
SIRCS
I
Sircs remote control signal input
4
NC
—
Not used
5
TU-DATA O
Serial data output to the tuner unit
6
T-MODE
I
Head position detect switch input terminal “L”: forward direction, “H”: reverse direction
7
REG-CON
O
Main system power supply on/off control signal output “H”: power on
8
C-CLK/TU-CLK
O
Serial data transfer clock signal output to the digital signal processor (at CD function)
Serial data transfer clock signal output to the tuner unit (at tuner function)
Serial data transfer clock signal output to the tuner unit (at tuner function)
9
SPK PROTECT
I
Protect on/off control signal input from the speaker protect circuit “L”: protect on
10
CD-DATA O
Serial data output to the digital signal processor
11
C-SQCK
O
Subcode Q data reading clock signal output to the digital signal processor
12
C-SQSO/
RDS-DATA
I
Subcode Q data input from the digital signal processor (at CD function)
Serial data input from the RDS decoder (at tuner function)
(RDS decoder is used for the AEP and UK models)
Serial data input from the RDS decoder (at tuner function)
(RDS decoder is used for the AEP and UK models)
13
HOLD
O
Automatic power control hold signal output to the RF amplifier
14
ALC
O
Automatic limiter control signal output to the recording/playback equalizer amplifier
“H”: limiter on
“H”: limiter on
15
CD-ON
O
Power supply on/off control signal output for the CD section (+5V)
LED drive signal output of the CD indicator “H”: CD power on (LED on)
LED drive signal output of the CD indicator “H”: CD power on (LED on)
16
REC-MUTE
O
Recording muting on/off control signal output to the recording/playback equalizer amplifier
“L”: muting on
“L”: muting on
17
TUNED
I
Automatic limiter control signal input from the tuner unit
18
C-SENSE
I
Internal status detection monitor input from the digital signal processor
19
C-LATCH
O
Serial data latch pulse signal output to the digital signal processor
20
L-MUTE
O
Line muting on/off control signal output to the recording/playback equalizer amplifier
“H”: muting on
“H”: muting on
21
REC/PB
O
Recording/playback selection signal output to the tape section
“L”: playback mode, “H”: recording mode
“L”: playback mode, “H”: recording mode
22
AMP-MUTE
O
Muting on/off control signal output to the power amplifier “H”: muting on
23
TU-COUNT
I
PLL serial data input from the tuner unit
24
H/P CHK
I
Headphone jack connection detection signal input terminal
“L”: no connected, “H”: headphone connected
“L”: no connected, “H”: headphone connected
25
TU-ON
O
Power supply on/off control signal output for the tuner section (+9.5V)
LED drive signal output of the TUNER indicator “H”: tuner power on (LED on)
LED drive signal output of the TUNER indicator “H”: tuner power on (LED on)
26
DSG
O
LED drive signal output of the DSG (Dynamic Sound Generator) indicator “H”: LED on
27
CD-SYNC
O
LED drive signal output of the CD SYNCHRO indicator “H”: LED on
28
SCK
O
Serial data transfer clock signal output to the electrical volume
29
SOL-CON
O
Trigger plunger on/off control signal output “H”: plunger on
30
MOT-CON
O
Capstan/reel motor on/off control signal output “H”: motor on
31
TU-CE
O
Chip enable signal output to the tuner unit
32
TC-SW
I
Half detect (side A and B) switch and cassette in detect switch input terminal (A/D input)
33
TRAY-SW
I
Disc tray open/close detect switch input terminal (A/D input)
“L”: disc tray open, “H”: disc tray close
“L”: disc tray open, “H”: disc tray close
34 to 36
KEY3 to KEY1
I
Key input terminal (A/D input)
37
SIMUKE
I
Destination setting terminal (A/D input)
35
HCD-M70
Pin No.
Pin Name
I/O
Description
38
RST
I
System reset signal input “L”: reset
For several hundreds msec. after the power supply rises, “L”: is input, then it changes to “H”
For several hundreds msec. after the power supply rises, “L”: is input, then it changes to “H”
39
EXTAL1
I
Main system clock input terminal (4.19MHz)
40
XTAL1
O
Main system clock output terminal (4.19MHz)
41
VSS
—
Ground terminal
42
XTAL2
O
System clock output terminal Not used
43
EXTAL2
I
System clock input terminal Not used
44
AVREF
I
Reference voltage (+5V) input terminal (for A/D conversion)
45
AVSS
—
Ground terminal (for A/D conversion)
46
VL
O
Liquid crystal display bias on/off control signal output
47 to 49
VLC3 to VLC1
—
Power supply terminal for the liquid crystal display bias
50 to 53
COM0 to COM3
O
Common drive signal output to the liquid crystal display
54 to 85
SEG0 to SEG31
O
Segment drive signal output to the liquid crystal display
86
C-RST
O
Reset signal output to the digital signal processor and motor/coil driver “L”: reset
87
AU-CE
O
Chip enable signal output to the electrical volume
88
SDA
O
Serial data output to the electrical volume
89
VDD
—
Power supply terminal (+5V)
90
NC
—
Not used
91
VSS
—
Ground terminal
92
TX
O
Sub system clock output terminal (32.768kHz)
93
TEX
I
Sub system clock input terminal (32.768kHz)
94
TRAY-CLOSE
O
Motor drive signal (close direction) output to the loading motor driver “H” active
95
TRAY-OPEN
O
Motor drive signal (open direction) output to the loading motor driver “H” active
96
TC-ON
O
LED drive signal output of the TAPE indicator “H”: LED on
97
AU-MUTE
O
Audio line muting on/off control signal output “H”: muting on
98
STAND-BY LED
O
LED drive signal output of the standby indicator “H”: LED on
99
WP
I
Wakeup control signal input
100
C-SCOR
I
Subcode sync (S0+S1) detection signal input from the digital signal processor
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