Sony HCD-LV100AV / LBT-LV100AV Service Manual ▷ View online
61
•
VIDEO BOARD IC505 CL680T-D1
(MPEG VIDEO/AUDIO DECODER, VIDEO SIGNAL PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
NC
O
Not used (open)
2
VSS
—
Ground terminal
3
CD-BCK
I
CD decode bit clock signal (2.8224 MHz) input from the CXD3008Q (IC101)
4
CD-DATA
I
CD decode data input from the CXD3008Q (IC101)
5
CD-LRCK
I
CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3008Q (IC101)
6
CD-C2PO
I
CD decode C2 error data input from the CXD3008Q (IC101)
7 to 9
NC
O
Not used (open)
10 to 15
MD0 to MD5
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC506)
16
VSS
—
Ground terminal
17
MD6
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC506)
18
VDD3
—
Power supply terminal (+3.3V)
19
MD7
I/O
Two-way data bus with the D-RAM (IC507) Data input from the program ROM (IC506)
20
VSS
—
Ground terminal
21
MD8
I/O
Two-way data bus with the D-RAM (IC507) Data output to the program ROM (IC506)
22
VDD3
—
Power supply terminal (+3.3V)
23 to 28
MD9 to MD14
I/O
Two-way data bus with the D-RAM (IC507) Data output to the program ROM (IC506)
29
MD15
I/O
Two-way data bus with the D-RAM (IC507)
30 to 36
NC
O
Not used (open)
37
MCE
O
Chip enable signal output to the program ROM (IC506)
38
MWE
O
Write enable signal output to the D-RAM (IC507)
39
VSS
—
Ground terminal
40
CAS
O
Column address strobe signal output to the D-RAM (IC507)
41
VDD3
—
Power supply terminal (+3.3V)
42
RAS0
O
Row address strobe signal output to the D-RAM (IC507)
43
RAS1
O
Row address strobe signal output terminal Not used (open)
44, 45
MA10, MA9
O
Address signal output to the program ROM (IC506)
46
MA8
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
47
VSS
—
Ground terminal
48
MA7
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
49
VDD3
—
Power supply terminal (+3.3V)
50 to 52
MA6 to MA4
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
53
VSS
—
Ground terminal
54
MA3
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
55
VDD3
—
Power supply terminal (+3.3V)
56 to 58
MA2 to MA0
O
Address signal output to the program ROM (IC506) and D-RAM (IC507)
59
PGIO7
I/O
Not used (open)
60
RESET
I
Reset signal input from the CD mechanism controller (IC502) “L”: reset
61
VDDMAX-IN
I
Fix the maximum input voltage each input terminal and in/out terminal
62 to 64
NC
O
Not used (open)
65
AGND-DAC
—
Ground terminal (for D/A converter)
66
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
67
COMPOS OUT
O
Composite video signal output terminal Not used (open)
68
AGND-DAC
—
Ground terminal (for D/A converter)
69
Y-OUT
O
Luminance video signal output terminal
70
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
71
AGND-DAC
—
Ground terminal (for D/A converter)
62
Pin No.
Pin Name
I/O
Description
72
RREF
I
Fix the video signal output level control
73
VREF
O
Reference voltage (+1.235V) output terminal
74
AVDD-DAC
—
Power supply terminal (+3.3V) (for D/A converter)
75
C-OUT
O
Chrominance video signal output terminal
76
AGND-DAC
—
Ground terminal (for D/A converter)
77
CLK-SEL0
I
GCK (pin
`⁄‚fi
) selection terminal “L”: external clock, “H”: internal clock (fixed at “H”)
78
CLK-SEL1
I
DA-XCLK (pin
*§
) selection (1) terminal Fixed at “H” in this set
79
CLK-SEL2
I
DA-XCLK (pin
*§
) selection (2) terminal Fixed at “H” in this set
80
VSS
—
Ground terminal
81
RESERVED
I
Selection the operation clock 42.336 MHz (fixed at “L”)
82
VDD3
—
Power supply terminal (+3.3V)
83
DA-EMP
O
Not used (open)
84
RESERVED
O
Not used (open)
85
AGND-PLL
—
Ground terminal (for PLL system)
86
DA-XCLK
I
Main reference clock signal (16.9344 MHz=384fs) from the D/A converter (IC509)
87
AVDD-PLL
—
Power supply terminal (+3.3V) (for PLL system)
88
PGIO4
I/O
Not used (open)
89
PGIO5
I/O
Not used (open)
90
PGIO6
I/O
Not used (open)
91
PGIO0
I/O
Not used (open)
92
PGIO8
I/O
Not used (open)
93
PGIO2/VSYNC/
CSYNC
O
Vertical synchronized signal output to the CD mechanism controller (IC502)
94
AVDD-PLL
—
Power supply terminal (+3.3V) (for PLL system)
95 to 97
NC
O
Not used (open)
98
AGND-PLL
—
Ground terminal (for PLL system)
99
VSS
—
Ground terminal
100
NC
O
Not used (open)
101
PGIO3/HSYNC
I/O
Not used (open)
102
VDD3
—
Power supply terminal (+3.3V)
103
PGIO1/VCK-OUT
I/O
Not used (open)
104
VSS
—
Ground terminal
105
GCK
I
Not used (open)
106
VCK-IN
I
Main clock for video signal processor input from the D/A converter (IC509) (27 MHz)
107
GCKOUT/DA-EMP
O
Not used (open)
108
DA-LRCK
O
Digital audio L/R sampling clock signal (44.1 kHz) output to the D/A converter (IC509)
109
VDDMAX-OUT
O
Fix the maximum output voltage (+5V) certain output terminal
110
DA-DATA
O
Digital audio data output to the D/A converter (IC509)
111
DA-BCK
O
Digital audio bit clock signal (2.8224 MHz) output to the D/A converter (IC509)
112
HD-OUT
O
Serial data output to the CD mechanism controller (IC502)
113
HRDY
O
Ready signal output to the CD mechanism controller (IC502)
114
HINT
O
Interrupt request signal output to the CD mechanism controller (IC502)
115
CDG-SCK
I/O
Not used (open)
116
VSS
—
Ground terminal
117
HCK
I
Serial data transfer clock signal input from the CD mechanism controller (IC502)
118
VDD3
—
Power supply terminal (+3.3V)
119
HD-IN
I
Serial data input from the CD mechanism controller (IC502)
63
Pin No.
Pin Name
I/O
Description
120
VDD3
—
Power supply terminal (+3.3V)
121
HSEL
I
Command selection signal input from the CD mechanism controller (IC502)
122
CDG-SDATA
I
Not used (fixed at “L”)
123
CDG-VFSY
I
Not used (fixed at “L”)
124
CDG-S0S1
I
Not used (fixed at “L”)
125 to 128
NC
O
Not used (open)
SECTION 7
EXPLODED VIEWS
64
NOTE:
•
•
-XX, -X mean standardized parts, so they may
have some differences from the original one.
have some differences from the original one.
•
Items marked “*” are not stocked since they
are seldom required for routine service. Some
delay should be anticipated when ordering these
items.
are seldom required for routine service. Some
delay should be anticipated when ordering these
items.
•
The mechanical parts with no reference number
in the exploded views are not supplied.
in the exploded views are not supplied.
•
Hardware (# mark) list and accessories and
packing materials are given in the last of this
parts list.
packing materials are given in the last of this
parts list.
•
Abbreviation
EA
EA
: Saudi Arabia model.
SP
: Singapore model.
MY
: Malaysia model.
IA
: Indonesian model.
The components identified by mark 0 or
dotted line with mark 0 are critical for safety.
Replace only with part number specified.
dotted line with mark 0 are critical for safety.
Replace only with part number specified.
7-1. CASE, BACK PANEL SECTION
Ref. No.
Part No.
Description
Remarks
Ref. No.
Part No.
Description
Remarks
1
1
2
#1
#1
#3
#3
#3
#3
M901
#3
#3
#3
#3
#3
#3
#3
#3
#2
not
supplied
supplied
not
supplied
supplied
Front panel
4
3
5
1
3-363-099-01 SCREW(CASE 3 TP2)
2
4-214-777-51 UPPER CASE
3
1-693-488-11 TUNER(FM/AM)
4
4-227-751-41 PANEL, BACK (MY,SP)
4
4-227-751-51 PANEL, BACK (EA)
4
4-227-751-71 PANEL, BACK (IA)
5
1-769-977-11 WIRE(FLAT TYPE) (13 CORE)
M901
1-763-072-11 FAN, D.C.
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