Sony HCD-HX9 Service Manual ▷ View online
41
HCD-HX9
/OTW 2
GVDD_B 1
PROTECTION
LOGIC
GATE
DRIVE
GVDD_A
36
BST_A
35
PVDD_A
34
OUT_A
33
GND
32
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
/SD 3
PWM_A 4
PWM_B 6
/RESET_AB 5
/RESET_CD 15
PWM_C 14
M1 13
M2 12
GND 11
GND 8
GND 9
VREG 10
OC_ZDJ 7
PROTECTION
&
RESET LOGIC
OLP
OTP
OTP
CB3C
TIMING
CONTROL
STUCK
DETECT
STUCK
DETECT
STUCK
DETECT
REGULATOR
STUCK
DETECT
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROTECTION
LOGIC
GVDD_C
PWM_D 16
VDD 17
18
GATE
DRIVE
BST_C
27
PVDD_C
26
OUT_C
25
GND
24
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
TIMING
CONTROL
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROTECTION
LOGIC
GATE
DRIVE
BST_B
28
PVDD_B
29
OUT_B
30
GND
31
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
TIMING
CONTROL
TIMING
CONTROL
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROTECTION
LOGIC
GATE
DRIVE
BST_D
20
GVDD_D
19
PVDD_D
21
OUT_D
22
GND
23
GATE
DRIVE
OVER CURRENT
FAULT
OVER CURRENT
FAULT
TIMING
CONTROL
TIMING
CONTROL
/HIZ_LS
/OCH
/OCL
/RESET
/HIZ_HS
/UVP
PROGRAMMABLE
CURRENT SENSE
TEMPERATURE
WARNING/ERROR
2
4
/HIZ_HS
4
/HIZ_LS
4
/OCH
4
/OCL
GVDD_D
GVDD_C
GVDD_B
GVDD_A
VREG
4
/RESET
VREG
UNDER
VOLTAGE
PROTECTION
POWER-UP
RESET
/UVP
GVDD_A
GVDD_D
GVDD_B
GVDD_C
VREG
IC707 CXD9845AM
42
HCD-HX9
1
EN
2
GND
3
FLG
4
IN
5
OUT
GATE
CONTROL
UVLO
THERMAL
SHUTDOWN
CURRENT
LIMIT
FLAG
DELAY
IN
1
SW
2
SS
5
ADJ
4
LATCH
&
DRIVER
ERROR AMP
COMPARATOR
OSCILLATOR
RESET
OVERCURRENT
PROTECTION
THERMAL
PROTECTION
REFERENCE
VOLTAGE
GND
3
ON/OFF
SOFT
START
PREG
+
+
+
–
–
CONSTANT
CURRENT
SOURCE
2
FB
1
VDD
4
VCC
5 DRAIN
8 SOURCE
7 SOURCE
3
CL
VCL
CLAMP CIRCUIT
(ILIMIT SETTING)
IN
ICL.LOW
VCL.OUT
ILIMIT VARIABLE
CIRCUIT
+
–
+
–
+
–
7.2V
+
–
2.4V
VCC UV
VCC OVP
OVERHEAT
PROTECTION
S
R
Q
Q
RESTARTING
TRIGGER
R
S
Q
Q
+
–
27%
22%
22%
FOR LIGHT LOAD
DETECTION INTERMITTENT
OSCILLATION CONTROL
GENERATOR
CLOCK
12kHz
MAXDC
5.7V
5.0V
5.0V
VDD UV
5.7V
REGULATOR
VDD CLAMP
CIRCUIT
6.6V
+
–
ILIMIT
CORRECTION
CIRCUIT
FOR
DRAIN CURRENT
DETECT
GATE DRIVER
POWER
MOSFET
AT TURNING ON
BLANKING PULSE
GENERATION CIRCUIT
– USB Board –
IC915 R5523N001B-TR-F
– USB POWER Board –
IC319 SI-8008TFE
– SUB POWER Board –
IC601 MIP2F20MS1SO
43
HCD-HX9
•
IC Pin Function Description
CD BOARD IC101 TC94A70FG-007 (S, D) (CD-MP3 PROCESSOR)
Pin No.
Pin Name
I/O
Description
1
AVSS3
-
Ground terminal
2
RFZi
I
RF ripple zero crossing signal input terminal
3
RFRP
O
RF ripple signal output terminal
4
SBAD/RFDC
O
Sub beam addition signal or RF peak detection signal output terminal Not used
5
FEi
O
Focus error signal output terminal Not used
6
TEi
O
Tracking error signal output terminal
7
TEZi
I
Tracking error zero crossing signal input terminal
8
AVDD3
-
Power supply terminal (+3.3 V)
9
FOo
O
Focus coil drive signal output terminal
10
TRo
O
Tracking coil drive signal output terminal
11
VREF
I
Reference voltage (+1.65V) input terminal
12
FMO
O
Sled motor drive signal output terminal
13
DMO
O
Spindle motor drive signal output terminal
14
VSSP3
-
Ground terminal
15
VCOi
I
VCO control voltage input terminal
16
VDDP3
-
Power supply terminal (+3.3 V)
17
VDD1
-
Power supply terminal (+1.5 V)
18
VSS
-
Ground terminal
19
FGiN
I
FG signal input terminal Not used
20
IO0 (/HSO)
I
Disc inner position detection signal input terminal
21
IO1 (/UHSO)
O
Not used
22
XVSS3
-
Ground terminal
23
XI
I
System clock input terminal (16.9344 MHz)
24
XO
O
System clock output terminal (16.9344 MHz)
25
XVDD3
-
Power supply terminal (+3.3 V)
26
DVSS3
-
Ground terminal
27
RO
O
Audio data (R-ch) output to the input selector
28
DVDD3
-
Power supply terminal (+3.3 V)
29
DVR
O
Reference voltage (+1.65V) output terminal
30
LO
O
Audio data (L-ch) output to the input selector
31
DVSS3
-
Ground terminal
32
VDDT3
-
Power supply terminal (+3.3 V)
33
VSS1
-
Ground terminal
34
VDD1
-
Power supply terminal (+1.5 V)
35
VDDM1
-
Power supply terminal (+1.5 V)
36
SRAMSTB
I
S-RAM standby mode control signal input terminal Fixed at "L" in this set
37
XRST
I
Reset signal input from the system controller "L": reset
38, 39
BUS0, BUS1
I
Serial data input from the system controller and USB controller
40
BUS2 (SO)
I
Serial data input from the system controller and USB controller
41
BUS3 (SI)
I
Serial data input from the system controller and USB controller
42
BUCK (CLK)
I
Serial data transfer clock signal input from the system controller and USB controller
43
XCCE
I
Chip enable signal input from the system controller and USB controller
44
TEST
I
Setting terminal for test mode Normally fixed at "L"
45
IRQ
I
Interrupt request signal input terminal Not used
46
AoUT3 (PO4)
O
Request signal output to the USB controller
47
AoUT2 (PO5)
O
Audio data output terminal Not used
44
HCD-HX9
Pin No.
Pin Name
I/O
Description
48
PIO0
O
Request signal output to the system controller and USB controller
49, 50
PIO1, PIO2
O
Not used
51
PIO3
I
Gate signal input from the USB controller
52
VSS1
-
Ground terminal
53
VDDT3
-
Power supply terminal (+3.3 V)
54
SBSY
O
Subcode block sync signal output to the system controller
55
SBOK/FOK
O
Not used
56
IPF
O
Not used
57
SFSY/LOCK
O
Not used
58
ZDET
O
Zero detection signal output terminal Not used
59
GPIN
I
Not used
60
MS
I
Microcomputer interface mode selection signal input terminal Fixed at "H" in this set
61
DOUT (PO6)
O
Digital audio data output terminal Not used
62
AOUT (PO7)
O
Audio data output terminal Not used
63
BCK (PO8)
O
Bit clock signal output terminal Not used
64
LRCK (PO9)
O
L/R sampling clock signal output terminal Not used
65
AIN (PI4)
I
Digital audio data input from USB controller
66
BCKi (PI5)
I
Bit clock signal input from the USB controller
67
LRCKi (PI6)
I
L/R sampling clock signal input from the USB controller
68
VDD1
-
Power supply terminal (+1.5 V)
69
VSS
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3 V)
72
Pdo
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifier for PLL loop filter
76
LPFo
O
Signal output from the operation amplifier for PLL loop filter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO filter output terminal
79
PVSS3
-
Ground terminal
80
SLCo
O
EFM slice level output terminal
81
RFi
I
RF signal input terminal
82
RFRPi
I
RF ripple signal input terminal
83
RFEQo
O
EFM slice level output terminal
84
VRo
O
Reference voltage (+1.65V) output terminal
85
RESiN
O
External resistor connection terminal
86
VMDiR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass filter terminal for RFEQO offset correction
88
AGCi
I
RF signal amplitude adjustment amplification input terminal
89
RFo
O
RF signal generation amplification output terminal
90
RVDD3
-
Power supply terminal (+3.3 V)
91
LDo
O
Laser diode on/off control signal output to the automatic power control circuit
"H": laser diode on
"H": laser diode on
92
MDi
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
-
Ground terminal
94
FNi2 (C)
I
Main beam (C) input from the optical pick-up block
95
FNi1 (A)
I
Main beam (A) input from the optical pick-up block
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