Sony HCD-HPZ7 / HCD-HPZ9 Service Manual ▷ View online
77
HCD-HPZ7/HPZ9
• IC Pin Function Description
BD BOARD IC201 CXD3014-201R (RF AMP, DSP, MP3)
BD BOARD IC201 CXD3014-201R (RF AMP, DSP, MP3)
Pin No.
Pin Name
I/O
Description
1
LRCK
O
L/R sampling clock signal output
2
LRCKI
I
L/R sampling clock signal input
3
PCMD
O
PCM data output
4
PCMDI
I
PCM data input
5
BCK
O
Bit clock signal output
6
BCKI
I
Bit clock signal input
7
XTACN
I
Oscillation circuit
8
XRST
I
System reset signal input
9
VSS
—
Internal digital ground
10
IREQ-MP3
O
Data transfer request signal output to the system controller
11
CLOCK
I
Serial data transfer clock input from the system controller
12
D ATA2
I
Serial data input from the system controller
13
XLAT-MP3
I
Serial data latch pulse input from the system controller
14
REQ-MP3
I
Data transfer request signal input from the system controller
15
ACK-MP3
O
Acknowledge signal output to the system controller
16
XLAT
I
Latch input from the system controller
17
VDD
—
Power supply (+2.5V)
18
SVSS
—
Internal digital ground
19
SVDD
—
Power supply (+2.5V)
20
SENS
O
SENS output to the system controller
21
WFCK
O
WFCK output (Not used)
22
XUGF
O
XUGF output (Not used)
23
XPCK
O
XPCK output (Not used)
24
GFS
O
GFS output (Not used)
25
C2PO
O
C2PO output (Not used)
26
SCOR
O
High output when the subcode sync, S0 or S1, is detected
27
VDD
—
Power supply (+2.5V)
28
COUT
I/O
Track number count signal input/output (Not used)
29
SVSS
—
Internal digital ground
30
SVDD
—
Power supply (+2.5V)
31
MIRR
I/O
Mirror signal input/output (Not used)
32
DFCT
I/O
Defect signal input/output (Not used)
33
FOK
I/O
Focus OK signal input/output (Not used)
34
VSS
—
Internal digital ground
35
VDD
—
Power supply (+2.5V)
36
VSS
—
Internal digital ground
37
LOCK
I/O
GFS is sampled at 460Hz; when GFS is high , this pin outputs a high signal
If GFS is low eight consecutive (Not used)
38
MDP
O
Spindle motor servo control output
39
SSTP
I
Disk innermost detection signal input
40
IOVSS1
—
Internal digital ground
41
SFDR
O
Sled drive output
42
SRDR
O
Sled drive output
43
TFDR
O
Tracking drive output
44
TRDR
O
Tracking drive output
45
FFDR
O
Focus drive output
46
FRDR
O
Focus drive output
78
HCD-HPZ7/HPZ9
Pin No.
Pin Name
I/O
Description
47
IOVDD1
—
I/O digital power supply (+3.3V)
48
AVDD0
—
Analog power supply (+3.3V)
49
AVSS0
—
Analog ground
50
E
I
E signal input
51
F
I
F signal input
52
TEI
I
Tracking error signal input to DSSP block
53
TEO
O
Tracking error signal output from RF amplifier block
54
FEI
I
Focus error signal input to DSSP block
55
FEO
O
Focus error signal output from RF amplifier block
56
VC
O
Center voltage output
57
A
I
A signal input
58
B
I
B signal input
59
C
I
C signal input
60
D
I
D signal input
61
AVDD4
—
Analog power supply (+3.3V)
62
RFDCO
O
RFDC signal output (Not used)
63
PDSENS
I
Reference voltage pin for PD (Analog ground)
64
AC_SUM
O
RFAC summing amplifier output
65
EQ_IN
I
Equalizer circuit input
66
LD
O
APC amplifier output
67
PD
I
APC amplifier input
68
RFC
I
Equalizer cut-off frequency adjustment pin
69
AVSS4
—
Analog ground
70
RFACO
O
RFAC signal output
71
RFACI
I
RFAC signal input or EFM signal input
72
AVDD3
—
Analog power supply (+3.3V)
73
BIAS
I
Asymmetry circuit constant current input
74
ASYI
I
Asymmetry comparator voltage input
75
ASYO
O
EFM full-swing output (Low = VSS, High = VDD)
76
VPCO
O
Wide-band EFM PLL charge pump output (Not used)
77
VCTL
I
Wide-band EFM PLL VCO2 control voltage input (connected to ground)
78
AVSS3
—
Analog ground
79
CLTV
I
Multiplier VCO1 control voltage input
80
FILO
O
Master PLL (slave = digital PLL) filter output
81
FILI
I
Master PLL filter input
82
PCO
O
Master PLL charge pump output
83
SVSS
—
Internal digital ground
84
SVDD
—
Power supply (+2.5V)
85
SSTB-MP3
I
Standby signal input from the system controller
86
VDD
—
Power supply (+2.5V)
87
VSS
—
Internal digital ground
88
TEST1
I
Test pin Normally ground
89
DATA
I
Serial data input from the system controller
90
CLK2
I
Serial clock input from the system controller
91
SVSS
—
Internal digital ground
92
SVDD
—
Power supply (+2.5V)
93
JTAGTOK
—
Internal digital ground
94
JTAGTDI
—
Internal digital ground
95
JTAGTDO
—
Not used
79
HCD-HPZ7/HPZ9
Pin No.
Pin Name
I/O
Description
96
JTAGTMS
—
Internal digital ground
97
TRST
—
Internal digital ground
98
VSS
—
Internal digital ground
99
VDD
—
Power supply (+2.5V)
100
IOVDD2
—
I/O digital power supply (+3.3V)
101
DOUT
O
Digital out output
102
TEST
I
Test pin Normally ground
103
TES1
I
Test pin Normally ground
104
IOVSS2
—
Internal digital ground
105
PLLVDD
—
Power supply (+2.5V)
106
PLLVSS
—
Internal digital ground
107
XVSS
—
Internal digital ground
108
XTAO
O
Crystal oscillation circuit output
109
XTAI
I
Crystal oscillation circuit input
110
XVDD
—
Master clock power supply (+2.5V)
111
AVDD1
—
Analog power supply (+3.3V)
112
AOUT1
O
Lch analog output
113
VREFL
O
Lch reference voltage
114
AVSS1
—
Analog ground
115
AVSS2
—
Analog ground
116
VREFR
O
Rch reference voltage
117
AOUT2
O
Rch analog output
118
AVDD2
—
Analog power supply (+3.3V)
119
IOVDD0
—
I/O digital power supply (+3.3V)
120
IOVSS0
—
Internal digital ground
80
HCD-HPZ7/HPZ9
Pin No.
Pin Name
I/O
Description
1
CD DISCSENS 2
I
DISC 4, 5 and DISC (+1) detect signal input
2
CD DISCSENS 1
I
DISC 1 to 3 detect signal input
3
STBY LED
O
LED drive signal output terminal (power)
4
SIRCS IN/WAKE
I
SIRCS signal input terminal
5
MP3 DATA OUT
O
Serial data output to the MP3 decoder
6
MP3 DATA IN
I
Serial data input from the MP3 decoder
7
MP3 CLK
O
Serial data transfer clock signal output to the MP3 decoder
8
BYTE
I
External data bus width select signal input terminal (connected to ground)
9
CNVSS
—
Ground terminal
10
XCIN
I
Sub system clock input terminal (32.768 kHz)
11
XCOUT
O
Sub system clock output terminal (32.768 kHz)
12
RESET
I
System reset signal input terminal “L”: reset For several hundreds msec.
after the power supply rises, “L” is input, then it changes to “H”
13
XOUT
O
Main system clock output terminal (16 MHz)
14
VSS
—
Ground terminal
15
XIN
I
Main system clock input terminal (16 MHz)
16
VCC
—
Power supply terminal (+3.3V)
17
NMI
I
Non-maskable interrupt signal input terminal (Not used)
18
RDS-CLK
O
RDS serial data transfer clock signal output terminal (only for AEP, UK, CET models)
19
CD SCOR
I
Subcode Q data request signal input terminal
20
AC-CUT
I
Power down detection signal input terminal “L”: power down
21
RDS DATA
I
RDS serial data input terminal (only for AEP, UK, CET models)
22
CD XRST
O
System reset signal output to the RF AMP
23
CD XLT
O
Latch pulse signal output to the RF AMP
24
MP3 ACK
I
Acknowledge signal input from the MP3 decoder
25
MP3 XLAT
O
Serial data latch pulse output to the MP3 decoder
26
MP3 REQ
O
Data transfer request signal output to the MP3 decoder
27
MP3 IREQ
I
Data transfer request signal input from the MP3 decoder
28
MP3 STB
O
Standby signal output to the MP3 decoder
29
IIC CLK
I/O
IIC data transfer clock signal input and output (Not used)
30
IIC DATA
I/O
IIC two-way data bus (Not used)
31
SDA
O
SDA signal output
32
SCL
O
SCL signal output
33
XTCN
O
Oscillator control signal output to the CD DSP
34
CD BD POWER
O
Power on/off control signal output for CD block
35
CD DATA
O
Serial data output to the CD DSP
36
CD SENS
I
Internal status (SENSE) input from the CD DSP
37
CD CLK
O
Serial data transfer clock signal output to the CD DSP
38
CD AMUTE
O
CD muting on/off control signal output terminal (Not used)
39
FL DATA
O
Serial output to the FL/LED driver
40
ELV E3/TRE A
I
ELV pulse input from the rotary encoder
41
ELV E2/TRE B
I
ELV dial pulse input from the rotary encoder
42
ELV E1/BASS A
I
ELV dial pulse input from the rotary encoder
43
ELV E0/BASS B
I
ELV dial pulse input from the rotary encoder
44
SW4 (8CM)
I
CD disc size detection (8cm) signal input terminal
45
SW3 (PUSH-CLOSE)
I
CD push-close switch input terminal
46
SW2-1 (CLOSE)
I
CD close switch input terminal
47
SW2-2 (LOD POSITION)
I
CD loading position switch input terminal
48
SW1 (OPEN)
I
CD open switch input terminal
MAIN BOARD IC306 M30624MGP-A56FPU0 (SYSTEM CONTROLLER)
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