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Model
HCD-GV6 HCD-GV8 LBT-GV6 LBT-GV8
Pages
91
Size
9.39 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hcd-gv6-hcd-gv8-lbt-gv6-lbt-gv8.pdf
Date

Sony HCD-GV6 / HCD-GV8 / LBT-GV6 / LBT-GV8 Service Manual ▷ View online

16
HCD-GV6/GV8
REC Bias Adjustment
   DECK B
Procedure:
1. Mode: Record
FUNCTION: VIDEO
2. Mode: Playback
3. Confirm playback the signal recorded in step 1 become speci-
fication values as follows.
If these values are out of specification values, adjust the RV341
(L-CH) and RV441 (R-CH) on the AUDIO board to repeat
steps 1and 2.
Specification values: Playback output of 315 Hz to playback
output of 10 kHz: 
±
 0.5 dB
Adjustment Location: AUDIO board
REC Level Adjustment
   DECK B
Procedure:
1. Mode: Record
FUNCTION: VIDEO
2. Mode: Playback
3. Confirm playback the signal recorded in step 1 become speci-
fication values as follows.
If these values are out of specification values, adjust the RV301
(L-CH) and RV351 (R-CH) on the MAIN board to repeat steps
1 and 2.
Specification values:
J701 PB level:  47.2 to 53.0 mV (– 24.3 to – 23.3 dB)
Adjustment Location: MAIN board
attenuator
set
MAIN board 
VIDEO AUDIO IN jack (J701)
L-CH, R-CH
1) 315 Hz
2) 10 kHz
50 mV (– 23.8 dB)
600 
blank tape
CN-123
AF OSC
+
set
recorded
portion
MAIN board
MD OUT jack (J701)
L-CH, R-CH
level meter
set
MAIN board
VIDEO AUDIO IN jack (J701)
L-CH, R-CH
315 Hz, 50 mV (– 23.8 dB)
blank tape
CS-123
600 
attenuator
AF OSC
+
set
recorded
portion
MAIN board
MD OUT jack (J701)
L-CH, R-CH
level meter
RV301
RV341
RV311
IC602
CN601
R L
 
RV441
PB LEVEL
 (L)
– DECK B –
REC BIAS
PB LEVEL (L)
– DECK A –
– AUDIO BOARD (Component Side) –
TAPE SPEED
RV1002
RV1001
(NORMAL)  (HIGH)
CN1001
– LEAF SW BOARD (Component Side) –
MD OUT
L/R
IC301
REC LEVEL
RV301
L-CH
RV351
R-CH
VIDEO
AUDIO IN
L/R
J701
– MAIN BOARD (Conductor Side) –
HCD-GV6/GV8
17
17
VIDEO SECTION
Frequency Adjustment
Connection:
Procedure:
1. Connect the frequency counter to TP508 (27 MHz) on VIDEO
board.
2. Turn the power ON.
3. Press the 
[FUNCTION]
 button to select the CD.
4. Adjust CT503 on the VIDEO board so that the frequency
counter reading 27.0 MHz 
±
 80 Hz at stop status.
Adjustment Location:
+
TP508 (27 MHz)
VIDEO board
frequency counter
IC505
IC507
TP508
(27 MHz)
CT503
VIDEO
Frequency
Adjustment
– VIDEO BOARD (Side A) –
Note:
1. CD Block is basically designed to operate without adjustment.  There-
fore, check each item in order given.
2. Use YEDS-18 disc (3-702-101-01) unless otherwise indicated.
3. Use an oscilloscope with more than 10 M
 impedance.
4. Clean the object lens by an applicator with neutral detergent when the
signal level is low than specified value with the following checks.
S-Curve Check
Procedure:
1. Connect oscilloscope to TP (FE) and TP (VC).
2. Connect between TP (FE1) and TP (VC) by lead wire.
3. Connect between TP (AGCCON) and TP  (GND)  by lead wire.
4. Turn the power ON.
5. Load a disc (YEDS-18) and actuate the focus search. (In con-
sequence of open and close the disc tray, actuate the focus
search)
6. Cofirm that the oscilloscope waveform (S-curve) is symmetri-
cal between A and B.  And confirm peak to peak level within
±
 1 Vp-p.
S-curve waveform
7. After check, remove the lead wire connected in step 2 and 3.
Note:
• Try to measure several times to make sure than the ratio of A : B
or B : A is more than 10 : 7.
• Take sweep time as long as possible and light up the brightness
to obtain best waveform.
RF  Level Check
Procedure:
1. Connect oscilloscope to TP (RF) and TP (VC).
2. Connect between TP (AGCCON) and TP (GND) by lead wire.
3. Turn the power ON.
4. Load a disc (YEDS-18) and press the
H
 
X
button to play.
5. Confirm that the oscilloscope waveform is clear and check RF
signal level is correct or not.
6. After check, remove the lead wire connected in step 2.
Note:
Clear RF signal waveform means that the shape “ ” can be clearly
distinguished at the center of the waveform.
CD SECTION
+
BD board
TP (FE)
TP (VC)
oscilloscope
A
B
symmetry
within 4 
±
 1 Vp-p
+
BD board
TP (RF)
TP (VC)
oscilloscope
(AC range)
VOLT/DIV: 200 mV
TIME/DIV: 500 ns
(with the 10: 1 probe 
in use)
level:
1.45 
±
 0.3 Vp-p
E-F Balance (1 Track Jump) Check
Procedure :
1. Connect oscilloscpe to TP (TE) and TP (VC).
2. Turn the power ON.
3. Load a disc (YEDS-18) and playback the number five track.
4. Press the
H
 
X
button. (Becomes the 1 track jump mode)
5. Confirm that the level B and A (DC voltage) on the oscillo-
scope waveform.
1 track jump waveform
Specified level:          
×
 100 = less than 
±
 22%
6. After check, remove the lead wire connected in step 1.
Checking Location:
A
B
+
BD board
TP (TE)
TP (VC)
oscilloscope
(DC range)
A (DC voltage)
center of 
waveform
B
0V
level = 1.3 
±
 0.6 Vp-p
symmetry
TP (AGCCON)
TP (RF)
TP (GND)
TP (FE)
IC103
IC102
IC101
TP (FE1)
TP (VC)
TP (TE)
– BD BOARD (Side B) –
HCD-GV6/GV8
18
18
SECTION  7
DIAGRAMS
7-1.
BLOCK  DIAGRAM  – CD SERVO Section –
CD MECHANISM CONTROLLER
IC502 (1/2)
A/D
CONVERTER
CH1OUTF
CH1OUTR
5
4
7
2
1
5
10
6
6
7
8
16
14
13
10
11
22
4
24
25
23
5
6
2
3
17
18
15
16
A
E
B
C
D
A
CD D+5V
CD D+5V
F
DETECTOR
A
B
C
D
RF
SUMMING
AMP
FOCUS
ERROR AMP
RF EQ
AMP
TRACKING
ERROR AMP
RFO
FE
RF AMP,
FOCUS/TRACKING ERROR AMP
IC103
TE
E
F
F I-V AMP
E I-V AMP
AUTOMATIC
POWER CONTROL
Q101
OPTICAL
TRANSCEIVER
IC781
OSC
BUFFER
IC104
CD DIGITAL OUT
OPTICAL
APC LD
AMP
APC PD
AMP
LD
LD
PD
LASER DIODE
RFAC
ASYO
ASYI
CTL2
FILTER
FILO
PCO
CLTV
FILI
DIGITAL PLL
ASYMMETRY
CORRECTOR
EFM
DEMODULATOR
DIGITAL SIGNAL PROCESSOR
IC101 (1/2)
MDP
DIGITAL
CLV
PROCESSOR
32K
RAM
ERROR
CORRECTOR
INTERNAL BUS
SQCK
SQSO
MUTE
EXCK
PCMD
DATA
BCK
LRCK
C2PO
C4M
XTSL
XTAO
XTAI
BCK
LRCK
WDCK
C2PO
CTL1
CTL2
MD2
DOUT
DIGITAL
OUT
D/A
DIGITAL
INTERFACE
CLOCK
GENERATOR
SUBCODE
PROCESSOR
SCOR
WFCK
XUGF
GFS
EMPH
SENSE
DATA
CLOK
XLAT
SBSO
SENSE CLK
SENSE
DSP CLK
DSP DATA
DSP LATCH
SE
TE
FE
RFDC
FOCUS/
TRACKING/SLED
SERVO DSP
FOCUS/TRACKING/SLED
PWM GENERATOR
SFDR
CH3FIN
CH4SIN
CH3RIN
CH3OUTF
CH3OUTR
CH2FIN
CH2RIN
CH1FIN
CH1RIN
20
MUTE
SRDR
TFDR
TRDR
FFDR
FRDR
SSTP
COUT
S101
(LIMIT)
ON: When the optical pick-up
       is inner position.
CD D+5V
MIRR,
DFCT, FOK
DETECTOR
SERVO AUTO
SEQUENCER
SERVO
INTERFACE
CPU INTERFACE
SCLK
TO CPU INTERFACE
FOK
MIRR
DFCT
CH4OUTF
CH4OUTR
M101
(SPINDLE)
MOTOR
DRIVE
XRST
LDON
DSP MUTE
MOTOR
DRIVE
COIL
DRIVE
CH2OUTF
CH2OUTR
COIL
DRIVE
M
M
M102
(SLED)
FOCUS/TRACKING COIL DRIVE,
SPINDLE/SLED MOTOR DRIVE
IC102
2-AXIS
DEVICE
(TRACKING)
(FOCUS)
DIGITAL SERVO
PROCESSOR
IC101 (2/2)
OPTICAL PICK-UP
BLOCK
(KSS-213DH)
LDON
21
HOLD SW
PD
(Page 19)
 SIGNAL PATH
: CD PLAY (ANALOG OUT)
: CD PLAY (DIGITAL OUT)
I-V AMP
12
11
13
14
CTRL1
CTRL2
CTL1
CTL2
SUBQ DATA
SUBQ CLK
SCOR
MCLK
33.8MHz
B
(Page 19)
DATA, BCK,
LRCK, C2PO
C
(Page 19)
TBL-L
TBL-R
M
TABLE MOTOR DRIVER
IC201
OUT1
OUT2
IN1
IN2
M201
(TABLE)
SYSTEM CONTROLLER
IC501 (1/4)
DISC TABLE
SENSOR
IC202
ENC3/UP-SW
S201
(UP)
T-SENS
XRST
MOTOR
DRIVE
RESET
DEVICE RESET
XRESET
33
31
32
29
30
34
19
8
40 41 39 43
22
20
21
26
TO SERVO AUTO
SEQUENCER
50
53 55
XPCK
12
52 54
49
48
25
76 77
66
71
16
69
72
67
65
17
64
63
2
14
79 80
15
7
4 6 5
10 11 13 68
3
3 5 4
1
18
36 37
10
28
2
12
77
27
11
61
68
59
65
63
ENC2/DISC-LED 69
9
1
7
3
LED DRIVE
Q201
D201
(DISC No.)
HCD-GV6/GV8
19
19
7-2.
BLOCK  DIAGRAM  – AUDIO/VIDEO CD Section –
PROGRAM ROM
IC506
• SIGNAL PATH
: CD PLAY (AUDIO)
: CD PLAY (VIDEO)
D/A
CONVERTER
INPUT
INTERFACE
CIRCUIT
OSC
BUFFER
IC504
LOW-PASS
FILER
IC101
BUFFER
Q502
LOW-PASS
FILER
MODE
CONTROL
TIMING CONTROL/
CLOCK GENERATOR
VIDEO FREQUENCY
(27MHz)
DIGITAL FILTER, 
D/A CONVERTER
IC509
MPEG VIDEO/AUDIO DECODER,
VIDEO SIGNAL PROCESSOR
IC505
14
11
VOUTL
VOUTR
R-CH
10
RSTB
17
18
19
20
21
9
7
24
1
DATA
BCK
LRCK
CD-ROM
INTERFACE
CIRCUIT
MPEG
SYSTEM
DECODER
MPEG
VIDEO
DECODER
VIDEO
PROCESS
CIRCUIT
CPU INTERFACE
AUDIO
INTERFACE
CIRCUIT
MPEG
AUDIO
DECODER
D-RAM/ROM INTERFACE
3
4
5
CD-DATA
C2PO
DATA
BCK
LRCK
DATA, BCK,
LRCK, C2PO
CD-BCK
CD-LRCK
6
CD-C2PO
MA0 – MA10
MD0 – MD15
D0 – D15
D0 – D15
A0 – A10
A0 – A8
384FSO
768FSO
4
MCKO
X503
27MHz
CT503
MD
XT2
XT1
37
14 13
29
28
38 42 40
60
69
75
113
110
111
108
106
HRDY
Y-OUT
86
DA-XCLK
VCK-IN
DA-DATA
DA-BCK
DA-LRCK
C-OUT
93
114 121
HSEL
112
HD-OUT
119
HD-IN
117
HCK
ML
8
MC
LEVEL
SHIFT
IC501
B
(Page 18)
DATA, CLK
D
(Page 22)
MCLK 33.8MHz
A
(Page 18)
CD-L
E
(Page 21)
(Page 18)
C
DIGITAL
FILTER,
NOISE
SHAPER
CIRCUIT
58 – 56, 54, 52 – 50, 48, 46 – 44
10 – 15, 17, 19, 21, 23 – 29
16 – 19, 22 – 26
A0 – A10
12 – 5, 27, 26, 23
D8 – D14
A11 – A17
25, 4, 28, 29, 3, 2, 30
D0 – D7
O0 – O7
A0 – A10
DQ1 – DQ16
ADDRESS BUS
DATA BUS
D-RAM
IC507
A0 – A8
13 – 15, 17 – 21
2 – 5, 7 – 10, 31 – 34, 36 – 39
WE
22
CE
RAS
LCAS
UCAS
CAS
RESET
HINT
DATA
CLK
RAS0
MWE
MCE
RESET
X501
10MHz
PGIO2/VSYNC/CSYNC
B.P.F.
B.P.F.
VIDEO
BUFFER
Q301
VIDEO
BUFFER
Q303
VIDEO
BUFFER
Q307
VIDEO
BUFFER
Q308
VIDEO
BUFFER
Q304
VIDEO AMP
IC401 (1/2)
VIDEO AMP
IC401 (2/2)
SHARPNESS
CONTROL SWITCH
Q306
SHARPNESS
FILTER
Q302
VIDEO MUTING
Q453
VIDEO MUTING
Q454
Y/C MIX
Q310
C
Y
5
8
4
1
1
2
3
4
J301
S VIDEO OUT
VIDEO SELECT
SWITCH,
VIDEO AMP
IC191
A, B, C
F
(Page 21)
10
6
8
1
3 5
2
J702
J804 (1/2)
VIDEO OUT
LOGIC
IN1
A B C
IN3
VOUT
IN4
CTLA
CTLB
CTLC
VIDEO
VIDEO IN
GAME
INPUT
VIDEO
CD MECHANISM CONTROLLER
IC502 (2/2)
22
32
21
20
33
31
23
24
CL680 RESET
CL680 HINT
CL680 HRDY
CL680 SEL
DATA1I
93
NT/PAL
TEST LED
CLK1
DATA1O
45
BUS
DF LATCH
34
SHARPNESS
65
VMUTE
29
30
DATA
CLK
CLK
DATA
XOUT
XIN
NTSC
AUTO
PAL
S501
SYSTEM SELECT
D502
(SELF DIAGNOSIS)
73
13
15
• R-ch is omitted due to same as L-ch.
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