DOWNLOAD Sony HCD-GT220 / HCD-GT440 / HCD-GT660 / MHC-GT220 / MHC-GT440 / MHC-GT660 Service Manual ↓ Size: 5.57 MB | Pages: 94 in PDF or view online for FREE

Model
HCD-GT220 HCD-GT440 HCD-GT660 MHC-GT220 MHC-GT440 MHC-GT660
Pages
94
Size
5.57 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hcd-gt220-hcd-gt440-hcd-gt660-mhc-gt220-mhc-gt440-.pdf
Date

Sony HCD-GT220 / HCD-GT440 / HCD-GT660 / MHC-GT220 / MHC-GT440 / MHC-GT660 Service Manual ▷ View online

HCD-GT220/GT440/GT660
61
Pin No.
Pin Name
I/O
Description
56
IPF
O
Not used
57
SFSY/LOCK
O
Not used
58
ZDET
O
Zero detection signal output terminal    Not used
59
GPIN
I
Not used
60
MS
I
Microcomputer interface mode selection signal input terminal    Fixed at “H” in this set
61
DOUT (PO6)
O
Digital audio data output terminal    Not used
62
AOUT (PO7)
O
Audio data output terminal    Not used
63
BCK (PO8)
O
Bit clock signal output to the USB controller
64
LRCK (PO9)
O
L/R sampling clock signal output terminal    Not used
65
AIN (PI4)
I
Digital audio data input from the USB controller
66
BCKi (PI5)
I
Bit clock signal input from the USB controller
67
LRCKi (PI6)
I
L/R sampling clock signal input from the USB controller
68
VDD1
-
Power supply terminal (+1.5V)
69
VSS
-
Ground terminal
70
AWRC
-
Not used
71
PVDD3
-
Power supply terminal (+3.3V)
72
PDO
O
Phase error margin signal between EFM signal and PLCK signal output terminal
73
TMAXS
O
TMAX detection signal output terminal    Not used
74
TMAX
O
TMAX detection signal output terminal
75
LPFN
I
Inverted signal input from the operation amplifi er for PLL loop fi lter
76
LPFo
O
Signal output from the operation amplifi er for PLL loop fi lter
77
PVREF
I
Reference voltage (+1.65V) input terminal
78
VCOF
O
VCO fi lter output terminal
79
PVSS3
-
Ground terminal
80
SLCo
O
EFM slice level output terminal
81
RFi
I
RF signal input terminal
82
RFRPi
I
RF ripple signal input terminal
83
RFEQo
O
EFM slice level output terminal
84
VRo
O
Reference voltage (+1.65V) output terminal
85
RESiN
O
External resistor connection terminal
86
VMDiR
O
Reference voltage (+1.65V) output terminal for automatic power control circuit
87
TESTR
O
Low-pass fi lter terminal for RFEQO offset correction
88
AGCi
I
RF signal amplitude adjustment amplifi cation input terminal
89
RFo
O
RF signal generation amplifi cation output terminal
90
RVDD3
-
Power supply terminal (+3.3V)
91
LDo
O
Laser diode on/off control signal output to the automatic power control circuit    
“H”: laser diode on
92
MDi
I
Light amount monitor input from the laser diode of optical pick-up block
93
RVSS3
-
Ground terminal
94
FNi2 (C)
I
Main beam (C) input from the optical pick-up block
95
FNi1 (A)
I
Main beam (A) input from the optical pick-up block
96
FPi2 (D)
I
Main beam (D) input from the optical pick-up block
97
FPi1 (B)
I
Main beam (B) input from the optical pick-up block
98
TPi (F)
I
Sub beam (F) input from the optical pick-up block
99
TNPC
O
External capacitor connection terminal
100
TNi (E)
I
Sub beam (E) input from the optical pick-up block
HCD-GT220/GT440/GT660
62
USB  R  BOARD  IC901  TMP92CD28AFG-6U5J (USB  CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
/RESET
I
Reset signal input from the system controller    “L”: reset
2
DI
I
Ready to send signal input from the system controller
3, 4
NO USE
O
Not used
5
G-3
I
Function selection signal input terminal    Fixed at “H” in this set
6
DVCC
-
Power supply terminal (+3.3V)
7 to 9
NO USE
O
Not used
10
DVSS
-
Ground terminal
11
DVCC
-
Power supply terminal (+3.3V)
12
RVOUT1
O
Reference voltage (+3.3V) output terminal
13, 14
RVIN
I
Reference voltage (+3.3V) input terminal
15
RVOUT2
O
Reference voltage (+3.3V) output terminal
16
DVCC
-
Power supply terminal (+3.3V)
17
DVSS
-
Ground terminal
18 to 25
D0 to D7
I/O
Two-way data bus with the S-RAM
26
DVSS
-
Ground terminal
27
DVCC
-
Power supply terminal (+3.3V)
28 to 35
D8 to D15
I/O
Two-way data bus with the S-RAM
36
A0
O
Address signal output terminal    Not used
37 to 43
A1 to A7
O
Address signal output to the S-RAM
44
DVSS
-
Ground terminal
45
DVCC
-
Power supply terminal (+3.3V)
46 to 54
A8 to A16
O
Address signal output to the S-RAM
55 to 58
BUS0 to BUS3
O
Serial data output to the CD-MP3 processor
59
/BUCK
O
Serial data transfer clock signal output to the CD-MP3 processor
60
/CCE
O
Chip enable signal output to the CD-MP3 processor
61
NO USE
O
Not used
62
DVSS
-
Ground terminal
63
DVCC
-
Power supply terminal (+3.3V)
64
RD
O
Output enable signal output to the S-RAM
65
WR
O
Write enable signal output to the S-RAM
66
SRLLB
O
Lower-byte control signal output to the S-RAM
67
SRLUB
O
Upper-byte control signal output to the S-RAM
68
NO USE
O
Not used
69
BOOT
I
Boot mode selection signal input terminal    “L”: boot mode    Fixed at “H” in this set
70
CS2
O
Chip select signal output to the S-RAM
71
LRCK
O
L/R sampling clock signal output to the CD-MP3 processor
72
AM1
I
Function mode selection signal input terminal    Fixed at “H” in this set
73
X2
O
System clock output terminal (9 MHz)
74
DVSS
-
Ground terminal
75
X1
I
System clock input terminal (9 MHz)
76
DVCC
-
Power supply terminal (+3.3V)
77
USBOC
I
Over current detection signal input terminal
78
USBPON
O
USB power (VBUS) on/off control signal output terminal    “H”: power on
79
D+
I/O
Two-way data (positive) bus with the USB connector
80
D-
I/O
Two-way data (negative) bus with the USB connector
81
AM0
I
Function mode selection signal input terminal    Fixed at “H” in this set
82
NO USE
O
Not used
83
DVSS
-
Ground terminal
84
DO
O
Clear to send signal output to the system controller
85
DATA
I
Audio data input from the CD-MP3 processor
86
CLOCK
I
Audio data transfer clock signal input from CD-MP3 processor
87
TXD1
O
Serial data output to the system controller
88
RXD1
I
Serial data input from the system controller
89
NO USE
O
Not used
HCD-GT220/GT440/GT660
63
Pin No.
Pin Name
I/O
Description
90
SDA
I/O
Two-way EEPROM IIC data bus terminal    Not used
91
SCL
I/O
Two-way EEPROM IIC clock bus terminal    Not used
92
BCK
O
Bit clock signal output to the CD-MP3 processor
93
DATA
O
Audio data output to the CD-MP3 processor
94
GATE
O
Gate signal output to the CD-MP3 processor
95
DVCC
-
Power supply terminal (+3.3V)
96
REQ
I
Request signal input from the CD-MP3 processor
97
ST-REQ
I
Request signal input from the CD-MP3 processor
98, 99
G-1, G-2
I
Function selection signal input terminal    Fixed at “H” in this set
100
DVSS
-
Ground terminal
HCD-GT220/GT440/GT660
64
MAIN  BOARD  IC901 
μPD78F1165GF-GTSTDA-GAS-AX (GT220/GT440) (SYSTEM  CONTROLLER)
 
     
μPD78F1165GF (S)-GAS-AX (GT660) (SYSTEM  CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
O-SYS-MUTE
O
Muting on/off control signal output terminal    “L”: muting on
2
O-SWR
O
Sub woofer speaker on/off relay drive signal output terminal (GT440/GT660)
3
O-FRONT-SP-RELAY
O
Power on/off control signal output for speaker relays
4
O-CD-POWER
O
Power on/off control signal output for CD block
5
O-POWER-RELAY
O
Power on/off relay drive signal output terminal    “H”: power on
6
CD XRST
O
Reset signal output to the CD-MP3 processor    “L”: reset
7
CD-M-MUTE
O
Muting signal output to the coil/motor driver
8
O-USB-POWER
O
Power on/off control signal output for USB block
9
I-USB-CTS (DI)
I
Clear to send signal input from the USB controller
10
O-USB-RTS (DO)
O
Ready to send signal output to the USB controller
11
O-USB-RESET
O
Reset signal output to the USB controller    “L”: reset
12
CD-BUCK
O
Serial data transfer clock signal output to the CD-MP3 processor
13
CD-CCE
O
Chip enable signal output to the CD-MP3 processor
14 to 17
CD-BUS3 (I/O) to 
CD-BUS0 (I/O)
I/O
Two-way data bus with the CD-MP3 processor
18
MP3 IREQ
I
Request signal input from the CD-MP3 processor
19
CD-SEL1
O
Data selection signal output terminal
20
EVSS1
-
Ground terminal
21
CD-SEL2
O
Data selection signal output terminal
22
O-LM-R
O
Loading motor control signal output terminal (reverse direction)
23
O-LM-F
O
Loading motor control signal output terminal (forward direction)
24
O-TM-R
O
Table motor control signal output terminal (reverse direction)
25
O-TM-F
O
Table motor control signal output terminal (forward direction)
26
I-CD-SENS
I
Disc table address sensor input terminal
27
I-OPEN-SW
I
Disc table open/close detection switch input terminal    “L”: open, “H”: close
28
O-LC72121-CE
O
Chip enable signal output to the tuner (FM/AM)
29
I-SBSY
I
Subcode block sync signal input from the CD-MP3 processor
30
EVDD1
-
Power supply terminal (+3.3V)
31
I-LV23004T-DI
I
Serial data input from the tuner (FM/AM)
32
O-LV23004T-CLK
O
Serial data transfer clock signal output to the tuner (FM/AM)
33
O-LV23004T-DO
O
Serial data output to the tuner (FM/AM)
34
I-TUNED
I
Tuning detection signal input from the tuner
35
I-AC-CUT
I
AC power off detection signal input terminal
36
O-STK-MUTE
O
Standby signal output to the power amplifi er (for front speaker)
37
O-USB-LED
O
LED drive signal output terminal for REC/ERASE (USB) indicator    “H”: LED on
38
O-G-LED
O
LED drive signal output terminal for GUITAR indicator    “H”: LED on
39
O-V-LED
O
LED drive signal output terminal for VOCAL indicator    “H”: LED on
40
O-B-LED
O
LED drive signal output terminal for BASE indicator    “H”: LED on
41
O-F-DATA
O
Serial data output to the electrical volume
42
I-USB-RXD (SI)
I
Serial data input from the USB controller
43
O-USB-TXD (SO)
O
Serial data output to the USB controller
44
O-P-DATA
O
Serial data output to the parametric equalizer (GT660)
45
O-AUDIO-CLK
O
Serial data transfer clock signal output to the electrical volume and parametric equalizer 
(GT660)    
Serial data transfer clock signal output to the electrical volume (GT220/GT440)
46
O-REC/PB
O
Deck-A/B selection and recording/playback selection signal output terminal    
“L”: deck-B and playback, “H”: deck-A and recording
47
AVREF1
I
Reference voltage (+3.3V) input terminal
48
O-REC-MUTE
O
Recording muting on/off control signal output terminal    “L”: muting on
49
O-BIAS
O
Recording bias on/off control signal output terminal    “H”: bias on
50
AVREF0
I
Reference voltage (+3.3V) input terminal
51
AVSS
-
Ground terminal
52
I-USB-MONI
I
USB power (VBUS) monitoring input terminal
53
I-SUFIX
I
Setting terminal for the destination
54
I-MODEL
I
Setting terminal for model discrimination
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