DOWNLOAD Sony HCD-GS200 / MHC-GS200 Service Manual ↓ Size: 7.2 MB | Pages: 64 in PDF or view online for FREE

Model
HCD-GS200 MHC-GS200
Pages
64
Size
7.2 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hcd-gs200-mhc-gs200.pdf
Date

Sony HCD-GS200 / MHC-GS200 Service Manual ▷ View online

41
41
HCD-GS200
7-16. Schematic Diagram  – POWER Section –
42
42
HCD-GS200
7-17. IC Block Diagrams
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
+
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
DVC
+
+
RW/ROM
VC
RW/ROM
DVC
+
3
A
B
C
D
B
C
A
A
A
B
C
D
B
C D
D
+
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
– CD Board –
IC103
CXA2581N-T4
IC101
CXD3068Q
CE
RFDC
ADIO
IGEN
ASYO
ASYI
RFAC
CLTV
FILO
FILI
PCO
BIAS
VCTL
V16M
VPCO
TE
ASYE
MD2
DOUT
LRCK
PCMD
BCK
EMPH
XTSL
XTAI
XTAO
SOUT
SOCK
XOLT
SQSO
SQCK
SCSY
SBSO
EXCK
XRST
MUTE
DATA
XLAT
CLOK
SENS
SCLK
ATSK
W
FCK
XUGF
XPCK
GFS
C2PO
SCOR
CAM
WDCK
COUT
MIRR
SE
FE
VC
TES1
TEST
FFDR
TRDR
TFDR
SRDR
SFDR
FSTO
SSTP
LOCK
PWMI
FOK
FRDR
MDP
DFCT
CLOCK
GENERATOR
ASYMMETRY
CORRECTOR
DIGITAL
PLL
CPU
INTERFACE
INTERFACE
CORRECTOR
PROCESSOR
SUB CODE
RAM
32K
DEMODURATOR
EFM
ERROR
D/A
DIGITAL
OUT
INTERFACE
SERVO
INTERFACE
SERVO
AUTO
MIRR
DFCT
FOK
SERVO
FOCUS
SERVO DSP
SERVO
SERVO
SLED
TRACKING
FOCUS PWM
GENERATOR
GENERATOR
GENERATOR
SLED PWM
TRACKING PWM
A/D
CONVERTER
OPAMP
ANALOG SW
PWM GENERATOR
DIGITAL
CLV
SERVO BLOCK
– MAIN Board –
IC401
BA6780
VIN2
FIN2
RIN2
CT2
VEE
FBIN-
FBIN+
OUT2+
OUT2-
VIN1
FIN1
REVERSIBLE DRIVER
FWD/REV CONTROLLER
COVERNER DRIVER
FWD/REV CONTROLLER
COVERNER
LOAD CURRENT
DETECTION
AMPLIFIER
COVERNER 
OUTPUT
REFERENCE
VOLTAGE OUTPUT
LOW VOLTAGE
OUTPUT
RIN1
IOUT
VEE
VEE
VCC
VREF
VREG
VCC
OUT1+
+-
OUT1-
18
17
16
15
1
2
3
4
5
6
7
8
9
14
13
12
11
10
43
HCD-GS200
7-18.
IC Pin Function Description
• IC104 TC94A20F-CX4 D/A Converter, MP3 Decoder (CD Board)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 to 34
35
36
37
38
39
40
41
42
43
44
45
46, 47
48
49, 50
51
52
53
54
55
I/O
I
I
I
I
I/O
I
O
O
O
O
I
I
I
I
I
I
I
O
O
I
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
Pin Name
RESET
MIMD
MICS/AD0
MILP/AD1
MIDIO
MICK
MIACK/AD2
VDDT
SDO
BCKO/AD3
LRCKO/AD4
SDI0
BCKIA
LRCKIA
SDI1/AD5
BCKIB/CE
LRCKIB/OE
VDD
STANDBY
VSS
VSSL
VRAL
LO
VDAL
VDAR
RO
VRAR
VSSR
TESTP
CSK
PO0/AD12 to PO3/AD09
VDDT
PO4/AD8
PO5/AD7
PO6/AD6
PO7
VSS
FI0/AD13
FI1/AD14/VDDM
FI2/WR
FI3/AD16
VSSM
PI0, PI1
VSS
PI2/IO2, PI3/IO3
PI4/IO4
VDD
PI5/IO5
BOOT/IO6
TXO/IO7
Description
Reset input terminal “L”: reset
Microcomputer interface mode selection input “H”: I2C, “L”: TSB (fixed at “H”)
Microcomputer interface chip select signal input (fixed at “L”)
Microcomputer interface latch pulse input (fixed at “L”)
Serial data input/output
Serial clock input
Microcomputer interface acknowledge signal output (open)
Power supply (3.3V) for digital circuit
Data output (open)
Bit output (open)
LR clock output (open)
Data input 0
Bit clock input A
LR clock input A
Data input 1 (fixed at “L”)
Bit clock input B (fixed at “L”)
LR clock input B (fixed at “L”)
Power supply (2.5V) for digital circuit
Standby mode control signal input “H”: STB, “L”: normal (fixed at “L”)
Ground for digital circuit
Ground for DAC Lch
Reference voltage terminal for DAC Lch
DAC Lch signal output
Power supply (2.5V) for DAC Lch
Power supply (2.5V) for DAC Rch
DAC Rch signal output
Reference voltage terminal for DAC Rch
Ground for DAC Rch
Terminal for test “H”: test mode, “L”: normal (fixed at “L”)
SPDIF signal output (open)
General purpose output (open)
Power supply (3.3V) for digital circuit
General purpose output (open)
General purpose output (open)
General purpose output (open)
Interrupt request signal output to the system control (IC501)
Ground for digital circuit
External interrupt signal input (fixed at “L”)
Power supply (2.5V) for the internal 1Mbit SRAM
Flag signal input 0 (fixed at “L”)
Flag signal input 1 (fixed at “L”)
Ground for the internal 1Mbit SRAM
General purpose input (fixed at “L”)
Ground for digital circuit
General purpose input (fixed at “L”)
General purpose input (fixed at “L”)
Power supply (2.5V) for digital circuit
General purpose input/SUBQ interface data input (fixed at “L”)
Terminal for test/SUBQ interface frame sync input (fixed at “L”)
Flag signal input 2/SUBQ interface block sync input (fixed at “L”)
44
HCD-GS200
Pin No.
56
57
58
59
60
61
62
63
64
I/O
O
I
O
I
O
Pin Name
VSSP
PDO
VCOI
VDDP
CKO
VDDX
XI
XO
VSSX
Description
Ground for VCO circuit
PLL phase error detection signal output
VCO control voltage input
Power supply (2.5V) for VCO circuit
External clock output
Power supply (2.5V) for oscillation circuit
Resonator terminal (input)
Resonator terminal (output)
Ground for oscillation circuit
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