DOWNLOAD Sony HCD-GS100 Service Manual ↓ Size: 6.36 MB | Pages: 61 in PDF or view online for FREE

Model
HCD-GS100
Pages
61
Size
6.36 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hcd-gs100.pdf
Date

Sony HCD-GS100 Service Manual ▷ View online

41
41
HCD-GS100
7-16. Schematic Diagram  – POWER Section –
42
42
HCD-GS100
7-17. IC Block Diagrams
– CD Board –
TE
RFDC
CE
IGEN 
AVSS0 
ADIO 
AVDD0
CLTV
FILO
AVSS3
VSS
AVDD3
DOUT
VDD
PCO
FILI
ASYO
ASYI
RFAC
BIAS
SSTP
DFCT
MIRR
MDP
LOCK
FOK
SFDR
VSS
TEST
FRDR
FE
VC
COUT
SE
XTSL
TES1
SRDR
TFDR
FFDR
TRDR
2
1
70
71
68
69
66
67
64
65
62
61
63
73
74
72
75
76
77
78
79
80
4
XRST
3
SQCK
SQSO
5
9
8
7
6
56
60
53
54
55
59
57
58
51
52
48
49
50
47
44
45
46
43
41
42
XLAT
CLOK
SENS
SYSM
DATA
XUGF
XPCK
GFS
C2PO
WFCK
10 11 12 13 14 15 16 17 18 19 20
21
22
23
24
25
26
32
33
30
31
36
37
34
35
39
40
38
28
27
29
SPOA
ATSK
SCLK
VDD
SCOR
SPOB
XLON
XTAI
XVDD
EMPH
AVDD1
AOUT1
AIN1
XTAO
XVSS
AIN2
AOUT2
AVDD2
RMUT
LOUT2
LOUT1
BCK
LRCK
PCMD
LMUT
AVSS1
AVSS2
CPU
INTERFACE
SERVO AUTO
SEQUENCER
SERIAL IN
INTERFACE
OVER SAMPLING
DIGITAL FILTER
3rd ORDER
NOISE SHAPER
PWM
PWM
EFM
DEMODULATOR
TIMING
LOGIC
DIGITAL
OUT
D/A
INTERFACE
DIGITAL
PLL
ASYMMETRY
CORRECTOR
CLOCK
GENERATOR
MIRR, DFCT,
FOK
DETECTOR
DIGITAL
CLV
SUBCODE
PROCESSOR
SERVO
INTERFACE
SERVO DSP
FOCUS
SERVO
TRACKING
SERVO
SLED
SERVO
PWM GENERATOR
FOCUS PWM
GENERATOR
TRACKING
PWM GENERATOR
SLED PWM
GENERATOR
16K
RAM
ERROR
CORRECTOR
INTERNAL BUS
A/D
CONVERTER
OPERATIONAL
AMPLIFIER
ANALOG SWITCH
LEVEL SHIFT
INTERFACE
INTERFACE
INTERFACE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
20
21
22
23
24
25
26
27
28
19
18
17
16
15
F
R
R
F
F
R
R
F
R
R
F
F
MUTE
THERMAL
SHUTDOWN
VREFOUT
VREFIN
POWVCC
CH1FIN
CH1RIN
CH2FIN
CH2RIN
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
CAP
AIN1
CAP
AIN2
GND
PRFVCC
MUTE
POWVCC
CH4SIN'
CH4SIN
CH4BIN
CH3FIN
CH3RIN
CH3OUTR
CH3OUTF
CH4OUTR
CH4OUTF
CAP
AIN3
GND
IC101 CXD3017Q
IC102 BA5974FP-E2
IC103 CXA2581N-T4
RW/ROM
RW/ROM
EQ ON/OFF
VOFST
VOFST
DVC
VC
VC
VC
RW/ROM
VC
DVC
30
29
28
+
+
DVC
VCC
DVC
27
26
25
24
RW/ROM
EQ
23
22
21
20
19
RFAC
VCA
VCC
+
DVC
+
+
RW/ROM
VC
RW/ROM
DVC
+
3
A
B
C
D
B
C
A
A
A
B
C
D
B
C D
D
+
1
2
APC AMP
5
6
7
8
9
4
RFAC
SUMMING
AMP
RW/ROM
APC-OFF
(Hi-Z)
RW/ROM
(H/L)
VOFST
VC
RW/ROM
+
10
11
GM
GM
18
17
16
B
D
A
C
13
14
15
12
EQ IN
LD
PD
GND
A
B
C
D
AC SUM
E
F
DVCC
DVC
RFAC
SW
DC OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE BAL
TE
FEI
FE
– MAIN Board –
    IC401 BA6780
VIN2
FIN2
RIN2
CT2
VEE
FBIN-
FBIN+
OUT2+
OUT2-
VIN1
FIN1
REVERSIBLE DRIVER
FWD/REV CONTROLLER
COVERNER DRIVER
FWD/REV CONTROLLER
COVERNER
LOAD CURRENT
DETECTION
AMPLIFIER
COVERNER 
OUTPUT
REFERENCE
VOLTAGE OUTPUT
LOW VOLTAGE
OUTPUT
RIN1
IOUT
VEE
VEE
VCC
VREF
VREG
VCC
OUT1+
+-
OUT1-
18
17
16
15
1
2
3
4
5
6
7
8
9
14
13
12
11
10
43
HCD-GS100
7-18. IC Pin Function Description
• CD Board  IC101  CXD3017Q
(Digital Signal Processor, Digital Servo Processor, Digital Filter, D/A Converter)
Pin No.
Pin Name
I/O
Description
1
SQSO
O
Subcode Q data output to the system controller (IC801)
2
SQCK
I
Subcode Q data reading clock signal input from the system controller (IC801)
3
XRST
I
System reset signal input from the system controller (IC801)    “L”: reset
4
SYSM
I
Analog line muting on/off control signal input terminal    “H”: line muting on
Not used (fixed at  “L”)
5
DATA
I
Command serial data input from the system controller (IC801)
6
XLAT
I
Command latch pulse input from the system controller (IC801)
7
CLOK
I
Command serial data transfer clock signal input from the system controller (IC801)
8
SENS
O
Internal status monitor output to the system controller (IC801)
9
SCLK
I
SENSE serial data reading clock input from the system controller (IC801)
10
VDD
Power supply terminal (+5V) (digital system)
11
ATSK
I/O
Input pin for anti-shock    Not used (fixed at  “L”)
12
SPOA
I
Microcomputer escape interface input A terminal    Not used (fixed at  “L”)
13
SPOB
I
Microcomputer escape interface input B terminal    Not used (fixed at  “L”)
14
XLON
O
Microcomputer escape interface output terminal     Not used (open)
15
WFCK
O
WFCK output terminal     Not used (open)
16
XUGF
O
Not used (open)
17
XPCK
O
Not used (open)
18
GFS
O
Not used (open)
19
C2PO
O
Not used (open)
20
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller (IC801)
21
COUT
I/O
Numbers of track counted signal input/output terminal    Not used (open)
22
MIRR
I/O
Mirror signal input/output terminal    Not used (open)
23
DFCT
I/O
Defect signal input/output terminal    Not used (open)
24
FOK
I/O
Focus OK input/output terminal    Not used (open)
25
LOCK
I/O
GFS is sampled by 460 Hz    “H” when GFS is “H”    Not used (open)
26
MDP
O
Spindle motor servo drive signal output to the BA5974FP (IC102)
27
SSTP
I
Limit in detect switch (S101) input terminal
28
SFDR
O
Sled servo drive PWM signal (+) output to the BA5974FP (IC102)
29
SRDR
O
Sled servo drive PWM signal (–) output to the BA5974FP (IC102)
30
TFDR
O
Tracking servo drive PWM signal (+) output to the BA5974FP (IC102)
31
TRDR
O
Tracking servo drive PWM signal (–) output to the BA5974FP (IC102)
32
FFDR
O
Focus servo drive PWM signal (+) output to the BA5974FP (IC102)
33
FRDR
O
Focus servo drive PWM signal (–) output to the BA5974FP (IC102)
34
VSS
Ground terminal (digital system)
35
TEST
I
Input terminal for the test (fixed at “L”)
36
TES1
I
Input terminal for the test (fixed at “L”)
37
XTSL
I
Input terminal for the system clock frequency setting    “L”: 45.1584 MHz, “H”: 22.5792 MHz
(fixed at “L” in this set)
38
VC
I
Middle point voltage (+2.5V) input from the CXA2581N (IC103)
39
FE
I
Focus error signal input from the CXA2581N (IC103)
40
SE
I
Sled error signal input from the CXA2581N (IC103)
41
TE
I
Tracking error signal input from the CXA2581N (IC103)
42
CE
I
Command chip enable signal input from the CXA2581N (IC103)
44
HCD-GS100
Pin No.
Pin Name
I/O
Description
43
RFDC
I
RF signal input from the CXA2581N (IC103)
44
ADIO
O
Monitor output of the A/D converter input signal    Not used (open)
45
AVSS0
Ground terminal (digital system)
46
IGEN
I
Stabilized current input for operational amplifiers
47
AVDD0
Power supply terminal (+5V) (digital system)
48
ASYO
O
Playback EFM full-swing output terminal
49
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
50
BIAS
I
Playback EFM asymmetry circuit constant current input terminal
51
RFAC
I
EFM signal input from the CXA2581N (IC103)
52
AVSS3
Ground terminal (digital system)
53
CLTV
I
Internal VCO control voltage input of the playback master PLL
54
FILO
O
Filter output for master clock of the playback master PLL
55
FILI
I
Filter input for master clock of the playback master PLL
56
PCO
O
Phase comparison output for master clock of the playback EFM master PLL
57
AVDD3
Power supply terminal (+5V) (digital system)
58
VSS
Ground terminal (digital system)
59
VDD
Power supply terminal (+5V) (digital system)
60
DOUT
O
Digital audio signal output to the DIGITAL OUT (CD)
61
LRCK
O
L/R sampling clock signal (44.1 kHz) output terminal    Not used (open)
62
PCMD
O
D/A interface serial data output terminal    Not used (open)
63
BCK
O
Bit clock signal (2.8224 MHz) output terminal    Not used (open)
64
EMPH
O
De-emphasis control signal output terminal    Not used (open)
65
XVDD
Power supply terminal (+5V) (crystal oscillator system)
66
XTAI
I
System clock input terminal (16.9344 MHz)
67
XTAO
O
System clock output terminal (16.9344 MHz)
68
XVSS
Ground terminal (crystal oscillator system)
69
AVDD1
Power supply terminal (+5V) (analog system)
70
AOUT1
O
L-ch analog audio signal output terminal
71
AIN1
I
L-ch operational amplifiers input terminal
72
LOUT1
O
L-ch line output terminal
73
AVSS1
Ground terminal (analog system)
74
AVSS2
Ground terminal (analog system)
75
LOUT2
O
R-ch line output terminal
76
AIN2
I
R-ch operational amplifiers input terminal
77
AOUT2
O
R-ch analog audio signal output terminal
78
AVDD2
Power supply terminal (+5V) (analog system)
79
RMUT
O
R-ch line muting on/off control signal output terminal    Not used (open)
80
LMUT
O
L-ch line muting on/off control signal output terminal    Not used (open)
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