Sony HCD-GN660 / HCD-GN770 / HCD-GX9000 / MHC-GN660 / MHC-GN770 / MHC-GX9000 Service Manual ▷ View online
HCD-GN660/GN770/GX9000
49
49
HCD-GN660/GN770/GX9000
7-24. PRINTED WIRING BOARD – SURROUND BOARD –
• See page 26 for Circuit Boards Location.
Ref. No. Location
D701
B-8
D702
D-9
D763
E-8
Q701
B-8
• Semiconductor
Location
2
3
4
5
6
7
8
9
10
A
1
B
C
D
E
F
G
1
13
R709
D702
Q701
E2,E3,E51
R707
R708
D701
E
CN701
FH760
F760
FH761
D763
CN703
CLP702
1
5
CLP701
JW764
CLP703
CLP700
NO704
3
1
JW795
JW766
JW766
JW765
JW767
JW768
JW768
JW769
JW796
JW796
C760
C761
B792
JW754
11
(11)
1-861-401-
MAIN
BOARD
(Page 36)
E
PRIMARY
BOARD
(Page 47)
L
POWER
TRANSFORMER
(Page 47)
M
SURROUND BOARD
HCD-GN660/GN770/GX9000
50
50
HCD-GN660/GN770/GX9000
7-25. IC Block Diagram
– BD Board –
IC251 BA5947FM
– DRIVER Board –
IC701, 712 BA6956AN
15
16
17
18
19
20
21
22
23
24
25
26
27
36
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
LEVEL
SHIFT
SHIFT
F
R
R
F
R
F
F
19k
6.5k
50k 50k
100k
50k
PIN3
10k
Vref
50k 50k
PIN26
(ch1, 2)
POW
VCC
(ch3, 4)
SW
Pre
Vcc
INTER
FACE
INTER
FACE
INTER
FACE
R
F
50k 50k
POW
VCC
MUTE
Vref
POW
VCC
R
F
10k
CH1PUTF
CH1OUTR
CH2OUTF
CH2OUTR
POWVCC
CNF4
GND
C-M
C-P
VG
CH2RIN
CH2FIN
CH1RIN
CH1FIN
SW
OPIN+
OPIN-
NC
CH4OUTR
CH4OUTF
CH3OUTF
CH3OUTR
POWVCC
MUTE
GND
GND
PREGND
CT
CH3RIN
CH3FIN
CH4IN
CH4CAPA
OUTVREF
DPOUT
TREVCC
NC
D
D
D
D
D
D
D
D
1
2
3
4
5
6
7
8
9
CONTROL LOGIC
TSD
VREF
OUT2
OUT1
RNF
VM
VCC
FIN
GND
RIN
– BD Board –
IC301 TC94A34FG-002
33
34
35
36
37
38
39
40
41
42
1
8
43
61
62
63
64
60
59
56
52
50
47
46
45
44
48
49
25
26
27
28
29
30
31
32
17
18
19
20
21
22
23
24
9
10
11
2
3
4
5
6
7
58
57
55
53
51
12
13
14
15
16
54
CS/RAS/ADO2
AD15/CAS/PD12
SDO3/OE
WE/SDO1
PIO7/B
US3/IO7
PIO6/FI3/B
US2/IO7
PIO5/FI2/B
US1/IO5
PIO4/FI1/B
US0/IO4
Bus
Switch
PO11/BUCK/AD14
PO10/CCE/AD13
PO9/AD12
PO08/AD11
Gener
al
In/Output P
or
t
Address Calc.
2sets
Y-
P
ointer
register
C-P
ointer
register
X-P
ointer
register
VDDM
SRMSTB
VDDT
AD10
AD9
ERAM
2k w
ord
CRAM
4k w
ord
CR
OM
4k w
ord
YRAM
4k w
ord
XRAM
4k w
ord
SRAM/
DRAM I/F
SRAM I/F
1Mbit
SRAM
X-Bus
Y
-Bus
PO07/AD7
PO06/AD6
PO05/AD5
AD8
VC0
Timing
Generator
PRAM
Instr
uction
Decoder
Prog
ram
Control
MCU
. I/F
register
XO • X1 • X2
Y0 •
Y1 •
Y2
MX
MY
MZ
MA
C
A0
A1
AX
A
Y
ALU
A2
A3
DIT
round & limit
round & limit
A
udio I/F
LRCKIA
BCKIA
SDI0
LRCKO
BCKO
SDO0
VSS
VDDT
MIACK
MICK
MIDIO
MILP
MICS
STANBY
RESET
VDDP
AD4/PO04
AD3/PO03
AD2/PO02
AD1/PO01
AD0/PO00
VSS
VDD
CK
O/PO13/AD16
VDDX
XO
TEST
VCOI
VSSX
XI
MIMD
VSSP
PIO3/IO3
PIO2/IO2
PIO1/SDI3/IO1
PIO0/SDI2/IO0
VSS
CKI/CLOCK/IRQ/FIO
VDD
TXO
SFSY/LRCKIB
SBSY/BCKIB
SDI1/D
A
T
A
POM
Sub code
I/F
CDP Cont
I/F
51
HCD-GN660/GN770/GX9000
7-26. IC Pin Function Descriptions
• IC101 CXD3059AR (RF AMP) (BD BOARD)
Pin No.
Pin Name
I/O
Description
1
MIRR
I/O
Mirror signal input/output(Not used)
2
DFCT
I/O
Defect signal input/output (Not used)
3
FOK
I/O
Focus OK signal input/output (Not used)
4
VSS
—
Internal digital ground
5
LOCK
I/O
Not used
6
MDP
O
Spindle motor servo control output
7
SSTP
I
Disk innermost detection signal input
8
IOVSS1
—
I/O digital ground
9
SFDR
O
Sled drive output
10
SFDR
O
Sled drive output
11
TFDR
O
Tracking drive output
12
TRDR
O
Tracking drive output
13
FFDR
O
Focus drive output
14
FFDR
O
Focus drive output
15
IOVDD1
—
I/O digital power supply
16
AVDD0
—
Analog power supply
17
AVSS0
—
Analog ground
18
NC
—
Not used
19
E
I
E signal input
20
F
I
F signal input
21
TEI
I
Tracking error signal input
22
TEO
O
Tracking error signal output
23
FEI
I
Focus error signal input
24
FEO
O
Focus error signal output
25
VC
I/O
Center voltage output from RF amplifier block
26
A
I
A signal input
27
B
I
B signal input
28
C
I
C signal input
29
D
I
D signal input A
30
NC
—
Not used
31
AVDD4
—
Analog power supply
32
RFDCO
O
RFDC signal output (Not used)
33
PDSENS
I
Reference voltage pin
34
AC_SUM
O
RFAC summing amplifier output
35
EQ_IN
I
Equalizer circuit input
36
LD
O
APC output
37
PD
I
APC input
38
NC
—
Not used
39
RFC
I
Equalizer cut-off frequency adjustment pin
40
AVSS4
—
Analog ground
41
RFACO
O
RFAC signal output
42
RFACI
I
RFAC signal input or EFM signal input
43
AVDD3
—
Analog power supply
44
BIAS
I
Asymmetry circuit constant current input
45
ASYI
I
Asymmetry comparator voltage input
46
ASYO
O
EFM full-swing output
47
VPCO
O
Not used
48
VCTL
I
Wide-band EFM PLL VCO2 control voltage input
52
HCD-GN660/GN770/GX9000
Pin No.
Pin Name
I/O
Description
49
AVSS3
—
Analog ground
50
CLTV
I
Multiplier VCO1 control voltage input
51
FILO
O
Master PLL (slave = digital PLL) filter output
52
FILI
I
Master PLL filter input
53
PCO
O
Master PLL charge pump output
54
AVDD5
—
Analog power supply
55
DDVROUT
O
DC/DC converter output
56
DDVRSEN
I
DC/DC converter output voltage monitor input
57
AVSS5
—
Analog ground
58
DDCR
I
DC/DC converter reset input
59
NC
—
Not used
60
BCKI
I
D/A interface bit clock input
61
PCMDI
I
D/A interface serial data input (2’s COMP, MSB first)
62
LRCKl
I
D/A interface LR clock input
63
LRCK
O
D/A interface LR clock output f = Fs
64
VSS
—
Internal digital ground
65
PCMD
O
D/A interface serial data output (2’s COMP, MSB first)
66
BCK
O
D/A interface bit clock output
67
VDD
—
Internal digital power supply
68
EMPH
O
High when the playback disc has emphasis, low it has not
69
EMPHI
I
High when de-emphasis is ON, low when input OFF
70
IOVDD2
—
I/O digital power supply
71
DOUT
O
Digital Out output
72
TEST
I
Test pin Normally ground
73
TES1
I
Test pin Normally ground
74
IOVss2
—
I/O digital ground
75
NC
—
Not used
76
XVSS
—
Master clock ground
77
XTAO
O
Crystal oscillation circuit output
78
XTAI
I
Crystal oscillation circuit input
79
XVDD
—
Master clock power supply
80
AVDD1
—
Analog power supply
81
AOUT1
O
Lch analog output
82
VREFL
O
Lch reference voltage
83
AVSS1
—
Analog ground
84
AVSS2
—
Analog ground
85
VREFR
O
Rch reference voltage
86
AOUT2
O
Rch analog output
87
AVDD2
—
Analog power supply
88
NC
—
Not used
89
IOVDD0
—
I/O digital power supply
90
RMUT
O
Rch “0” detection flag (Not used)
91
LMUT
O
Lch “0” detection flag (Not used)
92
NC
—
Not used
93
XTSL
I
Crystal selection input (Not used)
94
IOVSS0
—
I/O digital ground
95
XTACN
I
Oscillation circuit control
Self-oscillation when high, oscillation stop when low
96
SQSO
O
Subcode Q 80-bit and PCM peak and level data output (Not used)
97
SQCK
I
SQSO readout clock input
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