Sony HCD-EC50DC / MHC-EC50DC Service Manual ▷ View online
41
HCD-EC50DC
IC402 BA5947FM-E2
– BD83S Board –
1
LEVEL SHIFT
MUTING
D
15
16
+
–
+
–
D
D
17
18
D
19
20
VREF
21
22
23
24
25
26
27
28
PREVCC
OPOUT
OUTVREF
CH4CAPA
CH4IN
CH3FIN
CH3RIN
GND
MUTE
POWVCC
CH3OUTR
CH3OUTF
CH4OUTF
CH4OUTR
OPIN
–
2
OPIN+
INTERFACE
14
13
D
12
11
D
10
9
8
7
6
CH2FIN
CH2RIN
GND
5
4
CH1FIN
CH1RIN
VREFIN
POWVCC
CH2OUTR
CH2OUTF
CH1OUTR
CH1OUTF
INTERFACE
D
D
3
SW
INTERFACE
IC203 BH18LB1WG-TR
1
VIN
2
GND
3
STBY
4
NC
5
VOUT
VOLTAGE
REFERENCE
THERMAL
PROTECTION
OVER CURRENT
PROTECTION
CONTROL
BLOCK
– P-AMP Board –
IC202 STK432-070
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
+
ch.1
+
ch.2
LI+
LI-
NC
+VCC
ICC
LO+
LO-
+VP
-VP
RO+
RO-
-VCC
SUB
RI-
RI+
42
HCD-EC50DC
• IC Pin Function Description
BD83S BOARD IC201 CXD3014A-201R (RF AMP, DSP, MP3)
BD83S BOARD IC201 CXD3014A-201R (RF AMP, DSP, MP3)
Pin No.
Pin Name
I/O
Description
1
LRCK
O
L/R sampling clock signal output terminal
2
LRCKI
I
L/R sampling clock signal input terminal
3
PCMD
O
Serial data output terminal
4
PCMDI
I
Serial data input terminal
5
BCK
O
Bit clock signal output terminal
6
BCKI
I
Bit clock signal input terminal
7
XTACN
I
Oscillation circuit on/off switch control signal input from the system controller
“L”: oscillation stop, “H”: self-oscillation
8
XRST
I
System reset signal input from the system controller “L”: reset
9
VSS
—
Ground terminal
10
IREQ-MP3
O
MP3 data request signal output to the system controller
11
CLOK
I
CD serial data transfer clock signal input from the system controller
12
DATA2
I
MP3 serial data input from the system controller
13
XLAT-MP3
I
MP3 serial data latch pulse signal input from the system controller
14
REQ-MP3
I
MP3 data request signal input from the system controller
15
ACK-MP3
O
MP3 acknowledge signal output to the system controller
16
XLAT
I
CD serial data latch pulse signal input from the system controller
17
VDD
—
Power supply terminal (+1.8V)
18
SVSS
—
Ground terminal
19
SVDD
—
Power supply terminal (+1.8V)
20
SENS
O
Internal status (SENSE) signal output to the system controller
21
WFCK
O
WFCK output (Not used)
22
XUGF
O
XUGF output (Not used)
23
XPCK
O
XPCK output (Not used)
24
GFS
O
GFP output (Not used)
25
C2PO
O
C2PO output (Not used)
26
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller
27
VDD
—
Power supply terminal (+1.8V)
28
COUT
I/O
Track number count signal input/output (Not used)
29
SVSS
—
Ground terminal
30
SVDD
—
Power supply terminal (+1.8V)
31
MIRR
I/O
Mirror signal input/output (Not used)
32
DFCT
I/O
Defect signal input/output (Not used)
33
FOK
I/O
Focus OK signal input/output (Not used)
34
VSS
—
Ground terminal
35
VDD
—
Power supply terminal (+1.8V)
36
VSS
—
Ground terminal
37
LOCK
I/O
Not used
38
MDP
O
Spindle motor servo control signal output terminal
39
SSTP
I
Disc inner position detection signal input terminal
40
IOVSS1
—
Ground terminal
41
SFDR
O
Sled servo drive signal (+) output to the coil/motor driver
42
SRDR
O
Sled servo drive signal (–) output to the coil/motor driver
43
TFDR
O
Tracking servo drive signal (+) output to the coil/motor driver
44
TRDR
O
Tracking servo drive signal (–) output to the coil/motor driver
45
FFDR
O
Focus servo drive signal (+) output to the coil/motor driver
46
FRDR
O
Focus servo drive signal (–) output to the coil/motor driver
43
HCD-EC50DC
Pin No.
Pin Name
I/O
Description
47
IOVDD1
—
Power supply terminal (+3.3V)
48
AVDD0
—
Power supply terminal (+3.3V)
49
AVSS0
—
Ground terminal
50
E
I
E signal input from the optical pick-up block
51
F
I
F signal input from the optical pick-up block
52
TEI
I
Tracking error signal input terminal
53
TEO
O
Tracking error signal output terminal
54
FEI
I
Focus error signal input terminal
55
FEO
O
Focus error signal output terminal
56
VC
O
Middle point voltage output terminal
57
A
I
A signal input from the optical pick-up block
58
B
I
B signal input from the optical pick-up block
59
C
I
C signal input from the optical pick-up block
60
D
I
D signal input from the optical pick-up block
61
AVDD4
—
Power supply terminal (+3.3V)
62
RFDCO
O
RFDC signal output (Not used)
63
PDSENS
I
Reference voltage pin (Connected to ground)
64
AC_SUM
O
RFAC summing amplifier signal output terminal
65
EQ_IN
I
RF equalizer circuit input terminal
66
LD
O
Laser diode on/off control signal output to the automatic power control circuit
“L”: laser off, “H”: laser on
67
PD
I
Light amount monitor input from the optical pick-up block laser diode
68
RFC
I
Equalizer cut off frequency adjustment terminal
69
AVSS4
—
Ground terminal
70
RFACO
O
EFM signal output terminal
71
RFACI
I
EFM signal input terminal
72
AVDD3
—
Power supply terminal (+3.3V)
73
BIAS
I
Asymmetry circuit constant current input terminal
74
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
75
ASYO
O
Playback EFM full-swing output terminal
76
VPCO
O
Charge pump output terminal for broad-band EFM PLL (Not used)
77
VCTL
I
VCO2 control voltage input terminal for broad-band EFM PLL
78
AVSS3
—
Ground terminal
79
CLTV
I
VCO1 control voltage input terminal for multiplier
80
FILO
O
Filter output terminal for master PLL
81
FILI
I
Filter input terminal for master PLL
82
PCO
O
Charge pump output terminal for master PLL
83
SVSS
—
Ground terminal
84
SVDD
—
Power supply terminal (+1.8V)
85
SSTB-MP3
I
MP3 standby control signal input terminal “L”: standby (Connected to ground)
86
VDD
—
Power supply terminal (+1.8V)
87
VSS
—
Ground terminal
88
TEST1
I
Test terminal (Connected to ground)
89
DATA
I
CD serial data input from the system controller
90
CLK2
I
MP3 serial data transfer clock signal input from the system controller
91
SVSS
—
Ground terminal
92
SVDD
—
Power supply terminal (+1.8V)
93
JTAGTCK
—
Connected to ground
94
JTAGTDI
—
Connected to ground
44
HCD-EC50DC
Pin No.
Pin Name
I/O
Description
95
JTAGTDO
—
Not used
96
JTAGTMS
—
Connected to ground
97
TRST
—
Connected to ground
98
VSS
—
Ground terminal
99
VDD
—
Power supply terminal (+1.8V)
100
IOVDD2
—
Power supply terminal (+3.3V)
101
DOUT
O
Digital audio signal output terminal (Not used)
102
TEST
I
Test terminal (Connected to ground)
103
TES1
I
Test terminal (Connected to ground)
104
IOVSS2
—
Ground terminal
105
PLLVDD
—
Power supply terminal (+1.8V)
106
PLLVSS
—
Ground terminal
107
XVSS
—
Ground terminal
108
XTAO
O
System clock output terminal (16.9344 MHz)
109
XTAI
I
System clock input terminal (16.9344 MHz)
110
XVDD
—
Power supply terminal (+1.8V)
111
AVDD1
—
Power supply terminal (+3.3V)
112
AOUT1
O
L-ch analog audio signal output terminal
113
VREFL
O
L-ch reference voltage output terminal
114
AVSS1
—
Ground terminal
115
AVSS2
—
Ground terminal
116
VREFR
O
R-ch reference voltage output terminal
117
AOUT2
O
R-ch analog audio signal output terminal
118
AVDD2
—
Power supply terminal (+3.3V)
119
IOVDD0
—
Power supply terminal (+3.3V)
120
IOVSS0
—
Ground terminal
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