DOWNLOAD Sony HCD-EC50 Service Manual ↓ Size: 5 MB | Pages: 53 in PDF or view online for FREE

Model
HCD-EC50
Pages
53
Size
5 MB
Type
PDF
Document
Service Manual
Brand
Device
Audio
File
hcd-ec50.pdf
Date

Sony HCD-EC50 Service Manual ▷ View online

33
HCD-EC50
• IC Pin Function Description
   BD83S BOARD  IC201 CXD3014A-201R (RF AMP, DSP, MP3)
Pin No.
Pin Name
I/O
Description
1
LRCK
O
L/R sampling clock signal output terminal
2
LRCKI
I
L/R sampling clock signal input terminal
3
PCMD
O
Serial data output terminal
4
PCMDI
I
Serial data input terminal
5
BCK
O
Bit clock signal output terminal
6
BCKI
I
Bit clock signal input terminal
7
XTACN
I
Oscillation circuit on/off switch control signal input from the system controller
“L”: oscillation stop, “H”: self-oscillation
8
XRST
I
System reset signal input from the system controller “L”: reset
9
VSS
Ground terminal
10
IREQ-MP3
O
MP3 data request signal output to the system controller
11
CLOK
I
CD serial data transfer clock signal input from the system controller
12
DATA2
I
MP3 serial data input from the system controller
13
XLAT-MP3
I
MP3 serial data latch pulse signal input from the system controller
14
REQ-MP3
I
MP3 data request signal input from the system controller
15
ACK-MP3
O
MP3 acknowledge signal output to the system controller
16
XLAT
I
CD serial data latch pulse signal input from the system controller
17
VDD
Power supply terminal (+1.8V)
18
SVSS
Ground terminal
19
SVDD
Power supply terminal (+1.8V)
20
SENS
O
Internal status (SENSE) signal output to the system controller
21
WFCK
O
WFCK output (Not used)
22
XUGF
O
XUGF output (Not used)
23
XPCK
O
XPCK output (Not used)
24
GFS
O
GFP output (Not used)
25
C2PO
O
C2PO output (Not used)
26
SCOR
O
Subcode sync (S0+S1) detection signal output to the system controller
27
VDD
Power supply terminal (+1.8V)
28
COUT
I/O
Track number count signal input/output (Not used)
29
SVSS
Ground terminal
30
SVDD
Power supply terminal (+1.8V)
31
MIRR
I/O
Mirror signal input/output (Not used)
32
DFCT
I/O
Defect signal input/output (Not used)
33
FOK
I/O
Focus OK signal input/output (Not used)
34
VSS
Ground terminal
35
VDD
Power supply terminal (+1.8V)
36
VSS
Ground terminal
37
LOCK
I/O
Not used
38
MDP
O
Spindle motor servo control signal output terminal
39
SSTP
I
Disc inner position detection signal input terminal
40
IOVSS1
Ground terminal
41
SFDR
O
Sled servo drive signal (+) output to the coil/motor driver
42
SRDR
O
Sled servo drive signal (–) output to the coil/motor driver
43
TFDR
O
Tracking servo drive signal (+) output to the coil/motor driver
44
TRDR
O
Tracking servo drive signal (–) output to the coil/motor driver
45
FFDR
O
Focus servo drive signal (+) output to the coil/motor driver
46
FRDR
O
Focus servo drive signal (–) output to the coil/motor driver
34
HCD-EC50
Pin No.
Pin Name
I/O
Description
47
IOVDD1
Power supply terminal (+3.3V)
48
AVDD0
Power supply terminal (+3.3V)
49
AVSS0
Ground terminal
50
E
I
E signal input from the optical pick-up block
51
F
I
F signal input from the optical pick-up block
52
TEI
I
Tracking error signal input terminal
53
TEO
O
Tracking error signal output terminal
54
FEI
I
Focus error signal input terminal
55
FEO
O
Focus error signal output terminal
56
VC
O
Middle point voltage output terminal
57
A
I
A signal input from the optical pick-up block
58
B
I
B signal input from the optical pick-up block
59
C
I
C signal input from the optical pick-up block
60
D
I
D signal input from the optical pick-up block
61
AVDD4
Power supply terminal (+3.3V)
62
RFDCO
O
RFDC signal output (Not used)
63
PDSENS
I
Reference voltage pin (Connected to ground)
64
AC_SUM
O
RFAC summing amplifier signal output terminal
65
EQ_IN
I
RF equalizer circuit input terminal
66
LD
O
Laser diode on/off control signal output to the automatic power control circuit
“L”: laser off, “H”: laser on
67
PD
I
Light amount monitor input from the optical pick-up block laser diode
68
RFC
I
Equalizer cut off frequency adjustment terminal
69
AVSS4
Ground terminal
70
RFACO
O
EFM signal output terminal
71
RFACI
I
EFM signal input terminal
72
AVDD3
Power supply terminal (+3.3V)
73
BIAS
I
Asymmetry circuit constant current input terminal
74
ASYI
I
Playback EFM asymmetry comparator voltage input terminal
75
ASYO
O
Playback EFM full-swing output terminal
76
VPCO
O
Charge pump output terminal for broad-band EFM PLL (Not used)
77
VCTL
I
VCO2 control voltage input terminal for broad-band EFM PLL
78
AVSS3
Ground terminal
79
CLTV
I
VCO1 control voltage input terminal for multiplier
80
FILO
O
Filter output terminal for master PLL
81
FILI
I
Filter input terminal for master PLL
82
PCO
O
Charge pump output terminal for master PLL
83
SVSS
Ground terminal
84
SVDD
Power supply terminal (+1.8V)
85
SSTB-MP3
I
MP3 standby control signal input terminal  “L”: standby (Connected to ground)
86
VDD
Power supply terminal (+1.8V)
87
VSS
Ground terminal
88
TEST1
I
Test terminal (Connected to ground)
89
DATA
I
CD serial data input from the system controller
90
CLK2
I
MP3 serial data transfer clock signal input from the system controller
91
SVSS
Ground terminal
92
SVDD
Power supply terminal (+2.5V)
93
JTAGTCK
Connected to ground
94
JTAGTDI
Connected to ground
35
HCD-EC50
Pin No.
Pin Name
I/O
Description
95
JTAGTDO
Not used
96
JTAGTMS
Connected to ground
97
TRST
Connected to ground
98
VSS
Ground terminal
99
VDD
Power supply terminal (+1.8V)
100
IOVDD2
Power supply terminal (+3.3V)
101
DOUT
O
Digital audio signal output terminal ( Not used)
102
TEST
I
Test terminal (Connected to ground)
103
TES1
I
Test terminal (Connected to ground)
104
IOVSS2
Ground terminal
105
PLLVDD
Power supply terminal (+1.8V)
106
PLLVSS
Ground terminal
107
XVSS
Ground terminal
108
XTAO
O
System clock output terminal (16.9344 MHz)
109
XTAI
I
System clock input terminal (16.9344 MHz)
110
XVDD
Power supply terminal (+1.8V)
111
AVDD1
Power supply terminal (+3.3V)
112
AOUT1
O
L-ch analog audio signal output terminal
113
VREFL
O
L-ch reference voltage output terminal
114
AVSS1
Ground terminal
115
AVSS2
Ground terminal
116
VREFR
O
R-ch reference voltage output terminal
117
AOUT2
O
R-ch analog audio signal output terminal
118
AVDD2
Power supply terminal (+3.3V)
119
IOVDD0
Power supply terminal (+3.3V)
120
IOVSS0
Ground terminal
36
HCD-EC50
   PANEL BOARD IC701 MB90802-108 (SYSTEM CONTROLLER)
Pin No.
Pin Name
I/O
Description
1
P24
O
Power relay control signal ourput
2
P25
O
Amp control signal output
3
P26
O
System reset signal output to the RF AMP
4
P27
O
Control signal output to the PB/REC EQ AMP
5
P30/SO3
O
Serial data output to the MP3 decoder
6
P31/SC3
O
Serial data transfer clock signal output to the MP3 decoder
7
P32/SI3
I
Serial data input
8
P33/TMCK
O
Latch pulse signal output to the RF AMP
9
P34/IC0
I
Remote sencer signal input
10
P35/IC1
O
Serial data latch pulse output to the MP3 decoder
11
P36/OCU0
O
M-MUTE signal output to the MP3 decoder
12
P37/OCU1
O
Data transfer request signal output to the MP3 decoder
13
X0A/P90
O
Resonator output terminal (32.768kHz)
14
X1A/P91
I
Resonator input terminal (32.768kHz)
15
VCC
Power supply terminal (+3.3V)
16
VSS
Grounnd terminal
17
P40/LED0
O
STANDBY LED control signal output
18
P41/LED1
I
CD switch (SW3) input terminal
19
P42/LED2
I
CD switch (SW1) input terminal
20
P43/LED3
I
CD switch (SW2) input terminal
21
P44/LED4
O
Loading motor control signal output
22
P45/LED5/TOT0
O
Loading motor control signal output
23
P46/LED6/TOT1
O
Elevator up/down motor control signal output
24
P47/LED7/TOT2
O
Elevator up/down motor control signal output
25
P50/TIN0
I
CD chuck switch (SW7) input terminal
26
P51/TIN1
I
CD close switch (SW6) input terminal
27
P52/TIN2/PPG0
I
CD stoc switch (SW5) input terminal
28
P53/PPG1
I
CD open switch (SW8) input terminal
29
P54/SI0
I
Internal status (SENSE) input from the CD DSP
30
P55/SC0
O
Serial data transfer clock signal output to the CD DSP
31
P56/SO0
O
Serial data output to the CD DSP
32
AVCC
Power supply terminal (+3.3V)
33
P57/SI1
I
Data input from the the tuner
34
P76
O
Oscillator control signal output to the CD DSP
35
AVSS
Grounnd terminal
36
P60/AN0
I
Power detection signal input
37
P61/AN1
I
Key AD input1
38
P62/AN2
I
Key AD input2
39
P63/AN3
I
Tuner tuned status signal input
40
P64/AN4
I
Bias signal input from the bias oscillation circuit
41
P65/AN5/INT0
I
Key AD input3
42
P66/AN6/INT1
I
Power down detection signal input
43
P67/AN7/INT2
I
Subcode data request signal input terminal
44
VSS
Grounnd terminal
45
P70/AN8/INT3
Not used (open)
46
P71/AN9/SC1
O
Back light LED control signal output
47
P72/AN10/SO1
I
SUFIX signal input (Connected to +3.3V)
Page of 53
Display

Click on the first or last page to see other HCD-EC50 service manuals if exist.